chipforge

ChipForge AI

AI-powered FPGA development toolkit for Verilog simulation and design analysis.

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FPGA Development Workflow (MUST FOLLOW)

When user requests to design/implement a Verilog module, follow this workflow:

Phase 1: Knowledge Graph Setup

1. Initialize knowledge graph: chipforge-kg.exe init <project>
2. Add module nodes with properties (Signal type)
3. Add state machine nodes if applicable (StateTransition type)
4. Add relations between modules (RELATED, STATETRANSITION)

Phase 2: Implementation

1. Create project directory structure: rtl/, tb/
2. Write RTL code in rtl/ directory
3. Write testbench in tb/ directory (include $dumpfile and $dumpvars)

Phase 3: Verification Loop

1. Syntax check → Fix errors if any
2. Compile → Fix errors if any
3. Simulate → Generate VCD
4. Analyze VCD → Check waveforms
5. Fix issues → Repeat from step 8 if needed

Phase 4: Documentation

1. Add simulation results to knowledge graph (SignalExample type)
2. Link results to modules (EXAMPLES relation)
3. Report final status to user

Workflow Diagram

[Init KG] → [Write Code] → [Syntax Check]
                                ↓
                [Fix Code] ← [Errors?]
                    ↓            ↓ No
                   Yes      [Compile]
                    ↑            ↓
                [Fix Code] ← [Errors?]
                                ↓ No
                           [Simulate]
                                ↓
                          [Analyze VCD]
                                ↓
                [Fix Code] ← [Issues?]
                                ↓ No
                         [Update KG] → [Done]

IMPORTANT Rules

• NEVER skip syntax check before simulation
• ALWAYS generate VCD in testbench ($dumpfile, $dumpvars)
• ALWAYS analyze VCD after simulation
• ALWAYS update knowledge graph with results

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Available Tools (ONLY use these, do NOT guess other tool names)

Tool	Purpose
iverilog.exe	Verilog compiler
vvp.exe	Simulation runtime
vcd2wavedrom.exe	VCD to WaveJSON converter
chipforge-kg.exe	Knowledge graph CLI