Skill Claude CodeCodex
Standing, self-authorizing loop for the fork-gatekeeper identity — the maintainer of vibeic-eda (the composed EDA-tool image) and every individual forked EDA/PDK repo under the vibeic GitHub org (OpenROAD, yosys, magic, netgen, klayout, iverilog, verilator, ngspice, cocotb, pyuvm, sby, ihp-open-pdk, Trilinos, and the…
Skill Claude CodeCodex
Run formal property verification (FPV) on RTL by driving model-checkers such as SymbiYosys, Jasper, or VC Formal. Use when the user says "prove this", "formal verify", "model check", "run sby", or has SVA properties from assertion-gen that need to be proven or bounded.
Skill Claude CodeCodex
Generate HPS (Hard Processor System) integration for DE10-Nano FPGA verification. Replaces UART with direct memory-mapped register access from the ARM Cortex-A9 — approximately 100x faster, no external cables needed. Triggers when: 'HPS bridge', 'memory mapped FPGA', 'no UART', 'faster BIST', 'on-board test', 'HPS…
Skill Claude CodeCodex
Codify FPGA LED probe allocation patterns (instantaneous / pulse-stretched / sticky / byte-display) and produce an FPGA-top template with comment-table mapping (LED → signal → expected behaviour per test stage). Use when a fresh agent has to verify a chip on a DE10-Lite-class board with no scope and only the on-board…
Skill Claude CodeCodex
Auto-generate Quartus SignalTap II logic analyzer configurations for FPGA debugging. When to use: FPGA BIST fails and UART log isn't enough to diagnose the root cause. Generates .stp file that captures all DUT I/O signals, internal FSM state, and BIST engine state with configurable triggers. Triggers when…
Skill Claude CodeCodex
Run when the user says "have full test", "full test", "run the full audit", or asks to check D1/D2/D3. "Full test" is NOT just pytest — it is the four-part plugin health check: (full test) the whole test suite the CI way + chip-AGNOSTIC source guard, (D1) every program has a test, (D2) every flow step has a compliance…
Skill Claude CodeCodex
Infinite-loop single gatekeeper agent that OWNS main. Under the 2026-06-26 owner directive (direct-push, supersedes the 2026-06-17 PR-method) the maintainer ships its OWN fixes by direct commit + git push origin main with this same gate sequence applied PRE-PUSH (gatekeeperreview MERGEOK → Step-2.7 →…
Skill Claude CodeCodex
Translate C / C++ / SystemC algorithmic descriptions into synthesizable RTL via High-Level Synthesis. Use when the user says "HLS", "C to RTL", "C++ to Verilog", "Vitis HLS", "Catapult", "XLS", "algorithmic design", or provides a reference implementation in software and asks for hardware.
Skill Claude CodeCodex
Post-CTS and post-route hold violation fixing via buffer/delay cell insertion. CTS always introduces hold violations that must be fixed. Use when: 'hold violation', 'hold fix', 'hold slack', 'fix hold', 'negative hold slack', 'post-CTS hold', 'short path padding', or after CTS completes (Step 19).
Skill Claude CodeCodex
Closed-loop hardware debug methodology for half-duplex protocol ICs when BFM passes but real-silicon connecttest FAILs (Category B/C from the A/B/C extraction-gap analysis). Use after spec-to-rtl + flowcompliancecheck have all PASSed, the SOF has been burned to FPGA, and the host-side acceptance test (e.g.…
Skill Claude CodeCodex
Triage static and dynamic IR-drop and electromigration (EM) reports from power signoff tools (Voltus, RedHawk, PrimePower). Use when the user says "IR drop", "power grid", "dynamic voltage drop", "electromigration", "EM violation", "hotspot", "power signoff".
Skill Claude CodeCodex
Read BEFORE authoring or revising an L-layer emitter, an L-layer schema field, or a layer gate. Answers the three questions no program can decide for you — WHICH of the 27 layers a given fact belongs in (the layer that CONSUMES it, not any layer that mentions it), WHETHER the thing you are specifying is structural…
Skill Claude CodeCodex
The closed convergence loop for ANY benchmark subject — open-benchmark Evaluation, benchmark IC (doc→GDS), or IP-cell (doc→LEF/GDS). RUN the canonical front door, CLASSIFY every FAIL as flow / gate / tool, CONVERGE it by fixing the layer that owns it, PROVE the fix in the plugin cache against the real artefacts BEFORE…