vibeic

vibeic/vibe-ic

Plugin Claude Code

AI-native IC design plugins for Claude Code. Vibe Coding for ASIC: natural-language design intent → verified silicon.

vibeic/vibe-ic

Plugin Claude Code

AI-Native IC Design plugin for Claude Code — one install bundles and auto-registers the MCP-EDA server that wraps the open-source EDA toolchain and lab hardware. Two entry points into one Phase 1: (A) natural-language prompt/dialogue, or (B) existing design docs → layered design JSON (L-docs). Phase 2: RTL → lint →…

vibeic/vibe-ic

MCP server Claude CodeCodexCursor +2

MCP server "eda-tools" as configured in vibeic/vibe-ic. Runs ${CLAUDE_PLUGIN_ROOT}/mcp-eda/src/bootstrap.mjs with node. Needs 1 environment variable to run.

vibeic/vibe-ic

Agent

Runs Vibe-IC benchmark campaigns — "Run Benchmark Evaluation" (open benchmarks: VerilogEval / RTLLM / CVDP via /vibe-ic-benchmark) and "Benchmark IC" (the canonical ICs via /vibe-ic-all → /benchmark-verify). Commits + pushes results under benchmark-data/. When it finds a chip-AGNOSTIC plugin/MCP gap it AUTHORS the fix…

vibeic/vibe-ic

Agent

The AUTHOR half (alias) of the single repo-gatekeeper maintainer role. Authors deterministic chip-AGNOSTIC fixes into the plugin/MCP, self-verifies (reproduce + the cadence-correct suite the CI way), and ships them by DIRECT PUSH (2026-06-26 owner directive — direct commit + git push origin main, no PR ceremony; the…

vibeic/vibe-ic

Agent

The general-usage audit role. Runs the plugin against real benchmark IC projects, finds systematic chip-AGNOSTIC quality gaps, and files them as ORGANIC backlog issues for the Core Agent — then audits the closed fixes on real silicon and reopens any that are inadequate. Files backlog only; never checks in to…

vibeic/vibe-ic

Agent

The LAND half (alias) of the single repo-gatekeeper maintainer role — the sole merger of PRs and the assigner of versions at merge. It also authors (via the core-agent-loop half); there is NO author≠approver requirement. Quality is guaranteed by the GATES (machine checks + Step-2.7 adversarial §4.05 review + the…

vibeic/vibe-ic

Agent

Simulated end-user with zero IC-design knowledge. Speaks in product language — never uses technical vocabulary (CRC, opcode, register, FSM, MOSI, ADC, OTP, trim, VDD, etc.). Drives the IC Expert Agent (plain-language register) during Phase-1 training runs to produce a realistic non-expert dialogue transcript. Maps to…

vibeic/vibe-ic

Agent

Simulated senior IC designer with full datasheet / PDK / corner fluency. Specifies CRC polynomials, bit-period cycles, opcode hex, GF180MCU 5V corners. Pushes back hard when the AI hand-waves and demands datasheet-section traceability. Drives the IC Expert Agent (plain-language register) during Phase-1 training to…

vibeic/vibe-ic

Agent

Simulated hobbyist user with breadboard / Arduino-level IC vocabulary. Knows interface names (I2C, SPI, UART) and rough wire-level facts (pull-ups, 3.3V, addresses) but never bit-level / cycle-level detail. Drives the IC Expert Agent (plain-language register) during Phase-1 training to produce a hobbyist-voice…

vibeic/vibe-ic

Agent

The SINGLE maintainer role of the Vibe-IC repo — the unification of the former Core Agent (author) and Gatekeeper (land). It BOTH authors deterministic chip-AGNOSTIC fixes into the plugin/MCP AND gates every change (machine checks + Step-2.7 adversarial §4.05 review + serialized re-test-on-rebase), assigns the version…

vibeic/vibe-ic

Command

Codified after the v10627 / v10627-vendor false-PASS comparison. Inlined into every phase2 / phase2 / phase3 / phase23 / vibe-ic-all command so that any fresh agent invoking those commands sees the same hard rules.

vibeic/vibe-ic

Command

Run the complete Vibe-IC flow (Phase 1 → Phase 2 → Analog → Phase 3) via vibeiconeshotrunner. Auto-detects Path A vs B. AI-monitored + close-loop.

vibeic/vibe-ic

Command

Run any known open IC-design benchmark (VerilogEval-v2/Human, RTLLM, CVDP, …) the CORRECT way per the open-benchmark-methodology skill. Auto-routes to the right run-shape (A/B/C/D), sets up the run dir scaffold, points at the blind instructions, and invokes the scorer. Use when "run benchmark X", "score benchmark X"…

vibeic/vibe-ic

Command

Run Phase 1 (natural-language → L1-L27 JSON + human MD) via the deterministic phase1oneshotrunner. AI-monitored + close-loop.

vibeic/vibe-ic

Command

Run Phase 2 (L1-L27 → RTL → SOF → byte[6]=0xF2) via designoneshotrunner. AI-monitored + bounded RTL repair/retry.

vibeic/vibe-ic

Command

Chain /vibe-ic-phase2 → /vibe-ic-phase3 via phase23oneshotrunner (true chained orchestrator — delegates to designoneshotrunner.py + phase3oneshotrunner.py, not monolithic). AI-monitored + close-loop.

vibeic/vibe-ic

Command

Run Phase 3 (synth → PnR → GDS → DRC → LVS) via phase3oneshotrunner. AI-monitored + close-loop.

vibeic/vibe-ic

Hook

Runs when a session starts, executing post_install.sh and ic-expert-identity-session.sh via bash (2 commands). From vibeic/vibe-ic.

vibeic/vibe-ic

Hook

Runs when you submit a prompt, before the agent sees it, executing benchmark-keyword-skill-reminder.sh and ic-expert-identity-reminder.sh via bash (2 commands). From vibeic/vibe-ic.

vibeic/vibe-ic

Skill Claude CodeCodex

Plan and run analog / mixed-signal simulations — DC op, AC, transient, Monte Carlo, corner sweeps, PSRR/CMRR, noise — using ngspice, Xyce, Spectre, or HSPICE, and triage the results. Use when the user says "SPICE", "ngspice", "Monte Carlo", "corner simulation", "analog sim", "AC analysis", "transient", "PSRR", "CMRR"…

vibeic/vibe-ic

Skill Claude CodeCodex

Post-layout parasitic extraction + re-simulation for analog blocks — compares pre-layout vs post-layout specs. Use when the user says "post-layout resim", "extract and resimulate", "parasitic check", or at Step A7 of the analog track.

vibeic/vibe-ic

Skill Claude CodeCodex

Canonical reference doc for the Analog A1-A9 track — spec extraction → topology → netlist → corner sweep → layout → per-block PV (DRC/LVS) → post-layout resim → hardmacro → HIL. Used when an agent wants to walk the A1-A9 plan step-by-step. For unified one-command execution (deterministic runner + AI fall-through +…

vibeic/vibe-ic

Skill Claude CodeCodex

Package a verified analog block into a hardmacro (LEF abstract + Liberty timing + GDS + behavioral Verilog) for digital PnR integration. Use when the user says "package analog block", "generate hardmacro", "create LEF/Liberty", or at Step A7 of the analog track.