Getting it into your agent
It runs from inside its repository, so the clone comes first — what it calls does not travel with the file alone.
git clone --depth 1 https://github.com/vibeic/vibe-icnpx agentmods add skills/vibeic/vibe-ic/fpga-hps-bridgeWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/skills/vibeic/vibe-ic/fpga-hps-bridge)<a href="https://agentmods.dev/skills/vibeic/vibe-ic/fpga-hps-bridge"><img src="https://agentmods.dev/badge/skills/vibeic/vibe-ic/fpga-hps-bridge/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/skills/vibeic/vibe-ic/fpga-hps-bridge"><img src="https://agentmods.dev/badge/skills/vibeic/vibe-ic/fpga-hps-bridge.svg" alt="Reviewed on agentmods" width="80" height="20"></a>- NVIDIA SkillSpector pass
What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00103 | $0.02685 |
| Opus 5 | $0.00051 | $0.01342 |
| Sonnet 5 | $0.00021 | $0.00537 |
| Haiku 4.5 | $0.00010 | $0.00268 |
Grade A, and why
fpga-hps-bridge scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 11d ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 240 lines — stays where its author put it; the contents beside it link to each section on GitHub.
FPGA HPS Bridge Generator
Generate a complete HPS-to-FPGA bridge integration for Cyclone V SoC FPGA verification, enabling the ARM Cortex-A9 to control BIST engines via direct memory-mapped I/O instead of UART.
Generate (do NOT hand-paste the bridge or the register offsets)
The bridge RTL + the 16-entry register map are a FIXED, deterministic lookup —
paraphrasing a byte offset is a silent bug (the HPS /dev/mem read lands on the
wrong register and reports garbage with no error). Run the generator instead of
re-typing the files:
python3 ../../programs/fpga_hps_bridge_gen.py \
--ic <ic_name> --out <project_dir> \
[--bist <bist_module>] [--dut <dut_module>] \
[--chip-id 0xNN] [--version 0xNN] \
[--total-tests N] [--base 0xFF200000]
It emits all four artefacts verbatim and identically every run:
common_rtl/hps_bridge.sv, <ic>_hps_top.sv, hps_test.py, and
hps_register_map.md (the canonical 16-register table, offsets 0x00..0x3C).
--ic, the BIST/DUT module names, and the CHIP_ID/VERSION constants are
parameters — the generator is chip-AGNOSTIC. Invalid input (empty IC stem,
out-of-range constant) exits non-zero with a message; it never crashes or
emits a partial register map.
AI judgment still required (the generator does NOT do these): adapting the
BIST engine to your IC's coverage groups, wiring pin_cur / branch-coverage
tracking to your DUT, writing the HPS_INTEGRATION_GUIDE.md Qsys/Linux setup,
and deciding WHEN HPS is the right path vs UART (see When NOT to Use below).
When to Use
- UART is too slow — Stress testing 10K+ iterations takes hours over UART but seconds via HPS
- No external cable available — HPS talks to FPGA fabric internally, no USB-UART adapter needed
- Remote board access — SSH into DE10-Nano Linux, run tests remotely
- Regression testing — Batch run multiple ICs without cable swapping
- Production validation — Automated test on deployed boards
When NOT to Use
What ships with it
2 files beside SKILL.md in the same directory: the scripts, references and assets a skill reads on demand. Not counted in the per-session cost; read them before you install if any of them is executable.
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 11d ago First seen · 240 lines · 103 tokens per session scan A 7f5713160f8c
fpga-hps-bridge is a skill published in the GitHub repository vibeic/vibe-ic (23 stars, last pushed today), licensed Apache-2.0. It adds 103 tokens to every session and 2,685 once invoked, about $0.0005 per session on Opus 5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-30.
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