163 tagged eda, measured the same way as everything else here.
Browse within: ic-design 56asic 41data-science 30electronics 29leakage-detection 29machine-learning 29drc 17analog-design 15bom 15skill-library 15hardware-design 14kicad 12ai-skills 11design-review 11
Skill Claude CodeCodex
Extract structured specifications from electronic component datasheet PDFs — pinouts, electrical characteristics, peripherals, topology, and features. Cache extractions per project for consumption by schematic and PCB analyzers. Primary consumer infrastructure for kicad, emc, spice, and thermal analyzers. Use this…
Skill Claude CodeCodex
Search DigiKey for electronic components and download datasheets — primary source for prototype orders and the preferred API method for fetching datasheets. Find parts by keyword or MPN, check pricing/stock, download datasheets via API, analyze specifications. Sync and maintain a local datasheets directory — extract…
Skill Claude CodeCodex
Analyze KiCad projects and PDF schematics: schematics, PCB layouts, Gerbers, footprints, symbols, netlists, and design rules. Reviews designs for bugs, traces nets, cross-references schematic to PCB, extracts BOM data, checks DRC/ERC, DFM, power trees, and regulator circuits. Every finding carries a confidence label…
zhoushoujianwork/easyeda-agent
Skill Claude CodeCodex
Community EasyEDA Agent automation skill for EasyEDA Pro schematic and PCB work through the local easyeda-agent CLI/daemon/connector. Use when designing a board from scratch; inspecting, cleaning up, or safely refactoring an existing wired schematic; arranging multi-page functional modules; drawing page-scoped module…
Skill Claude CodeCodex
Use when creating, writing, reviewing, annotating, repairing, refactoring, or validating readable Verilog RTL, including synthesizable Verilog-2001 .v files, existing-RTL analysis, semantic comment annotation, testbench scaffold planning, ASIC-quality review, local or remote Vivado/xsim validation, evidence-backed…
Skill Claude CodeCodex
Drive an autonomous spec-to-board PCB design with the eda-agent MCP server (Altium Designer or EasyEDA Pro). Apply when the user asks to design a board/schematic from a requirement, wants an end-to-end autonomous design run, or mentions the design harness, designnextaction, design sessions, or spec-to-board. Requires…
Skill Claude CodeCodex
Use this skill for GitHub Copilot pull request and code reviews in oaslananka/kicad-mcp-pro. Review Python MCP server changes, KiCad adapter and tool-contract changes, tests, npm/package wrappers, Tauri/Rust desktop code, GitHub Actions, security controls, documentation, generated metadata, and compatibility/release…
Skill Claude CodeCodex
KiCad MCP manufacturing release workflow for Gerbers, drill files, BOM, pick-and-place, DFM, release evidence, and final human review.
Skill Claude CodeCodex
Drive a KiCad schematic to a professional, cosmetically clean state through a score → fix → render → verify loop using KiCad MCP Pro cosmetic tools.
Skill Claude CodeCodex
Transistor-level circuit design for one analog sub-block. Produces Spectre netlist with hand-calculation rationale. Use when designing a specific circuit block after architecture is defined.
Skill Claude CodeCodex
Crawl and analyze post-layout parasitic netlists without running SPICE. Answers "what's the effective resistance from node A to node B across this massive R mesh?", "inside the VREFN mesh, which device pins are electrically farthest apart?", "which nets have the worst coupling?", "where does settling bottleneck?" — by…
Skill Claude CodeCodex
Pre-simulation review and Spectre simulation verification for analog circuits. Reviews circuit netlist and testbench, runs simulation, produces margin report. Use after analog-design completes a netlist.
Skill Claude CodeCodex
Triage a copperhead GitHub issue, attempt reproduction, and check it against the spec. Use when the user asks to review an issue, e.g. /issue-review 42 or /issue-review .
Skill Claude CodeCodex
Update an OpenSpec change by revising its existing planning artifacts and keeping them coherent with one another. Use when the user wants to revise a change's plan, fold new decisions into it, or reconcile its artifacts after an edit. Never edits code.
Skill Claude CodeCodex
Review a copperhead pull request against the repo's invariants and spec workflow. Use when the user asks to review a PR, e.g. /pr-review 28 or /pr-review .
Skill Claude CodeCodex
EasyEDA component discovery, BOM review, LCSC/JLCPCB sourcing, pricing, availability, and part-risk workflow through EasyEDA MCP Pro.
Skill Claude CodeCodex
EasyEDA DRC/ERC, semantic ERC, power-tree, PCB constraints, production QA, export, and release-validation workflow through EasyEDA MCP Pro.
Skill Claude CodeCodex
End-to-end EasyEDA Pro workflow guidance for setup, inspection, controlled writes, exports, and reporting through EasyEDA MCP Pro.
Skill Claude CodeCodex
Circuit design and SPICE simulation assistant. Use when the user asks about circuit design, filters (low-pass, high-pass, bandpass, notch), amplifiers (inverting, differential, instrumentation, summing), voltage dividers, SPICE simulation, AC/DC/transient analysis, schematics, component selection, frequency response…
IntelligentElectron/universal-netlist
Skill Claude CodeCodex
ALWAYS use this skill when the user mentions: commit, push, PR, pull request, release, ship, tag, or any git workflow. This skill defines how to stage, commit, push, create PRs, and tag releases. It MUST be loaded before performing any git commit or push operation.
Skill Claude CodeCodex
Use this skill when the user asks to "design a PCB", "make a board", "build a PCB project", "order from JLCPCB", "create a schematic", "source LCSC parts", "wire up a board", "generate a PCB from a BOM", or any KiCad + JLCPCB workflow. Also use when working with .kicadpro or .kicadpcb files. Phase 1.6 handles project…
Skill Claude CodeCodex
Use when you need to create, write, review, annotate, or validate readable HLS, Vitis HLS, high-level synthesis, or HLS debug workflows.
Skill Claude CodeCodex
MANDATORY after ANY close-loop or real-case run where AI judgment recovered a previously-failing case — not just RTL authoring. Applies to EVERY step in the Vibe-IC flow: Phase 1 NL ingestion, Phase 2 spec-to-RTL / chiptop / synth / TB / rtlrepairretry / lint / conformance / audit, Phase 3 synth / PnR / CTS / DRC /…
Skill Claude CodeCodex
Closed-loop core-agent that fixes plugin issues filed by the field-agent. Invoke as a cron prompt; the loop polls the repo for ANY OPEN non-PR issue (new OR reopened — no label gating, no comment classifier), reproduces and fixes the bug chip-AGNOSTIC-ally, SELF-VERIFIES (reproduce + run the cadence-correct plugin…