agentmods.dev

Eriemon/verilog-generator

Agent skill for Verilog-2001 RTL generation and FPGA design workflows.

Open on GitHub
317Stars on the repository
1Mods indexed here, across every type
1mo agoLast push, which is what freshness is scored on
Apache-2.0Licence, which decides whether bodies are shown
Sort RelevanceRecently updatedFewest tokensSecurity gradeRepo starsStars this weekTop rated 1 mods

readable-verilog-generator

01

Eriemon/verilog-generator

Skill Codex

Use when creating, writing, reviewing, annotating, repairing, refactoring, or validating readable Verilog RTL, including synthesizable Verilog-2001 .v files, existing-RTL analysis, semantic comment annotation, testbench scaffold planning, ASIC-quality review, local or remote Vivado/xsim validation, evidence-backed…

not rated 317 +3 1mo ago A 77 tokens original Apache-2.0