Arcadia-1/virtuoso-bridge-lite
Skill Claude CodeCodex
Semantic cleanup and curation of Spectre/SPICE transistor netlists for analog review or reusable reference circuits. Use when Codex needs to understand generated ADE/PEX netlists, split DUT/testbench/run decks, optionally strip layout-derived MOS tail parameters by reasoning, rename random nodes/instances into…
Arcadia-1/virtuoso-bridge-lite
Skill Claude CodeCodex
Black-box optimization of design parameters using TuRBO or scipy. TRIGGER when the user wants to optimize, tune, size, sweep, or explore a design space to meet specs. This includes circuit sizing (W/L, bias, passives), finding optimal operating points, minimizing power-delay or noise-power tradeoffs, or any task where…
Arcadia-1/virtuoso-bridge-lite
Skill Claude CodeCodex
Run Cadence Spectre simulations remotely via virtuoso-bridge: upload netlists, execute, parse PSF results. TRIGGER when the user wants to run a SPICE/Spectre simulation from a netlist file, do transient/AC/PSS/pnoise analysis outside Virtuoso GUI, parse PSF waveform data, run multiple simulations in parallel across…
Arcadia-1/virtuoso-bridge-lite
Skill Claude CodeCodex
Operate Cadence Virtuoso through virtuoso-bridge: SKILL, CIW, schematic/symbol/layout, GDS, and ADE Maestro. Use spectre for standalone netlist-driven simulation.
Skill Claude CodeCodex
Dependency: ngspice skill (netlist execution, wrdata parsing). Model files are built in — the transistor-models skill is not required.
Skill Claude CodeCodex
Dependencies: system-installed ngspice, Python 3 with numpy ≥ 1.20, matplotlib ≥ 3.3, scipy ≥ 1.7 (NumPy 1.x and 2.x both supported).
Skill Claude CodeCodex
Sky130A open PDK workflow for ngspice-based analog simulation. Use when an agent needs to install or locate Sky130A via Volare/openpdks, run process-corner PVT simulations, run process Monte Carlo or mismatch-aware smoke tests, instantiate sky130fdpr devices, or validate Sky130A examples such as MOS Id-Vgs, ring…
Skill Claude CodeCodex
Complete PTM (Predictive Technology Model) MOSFET model library from mec.umn.edu/ptm, covering all nodes: bulk conventional 180/130/90/65nm, bulk HP/LP 45/32/22nm (BSIM4), and PTM-MG multi-gate FinFET 7/10/14/16/20nm (BSIM-CMG, HP + LSTP). No manual downloads required after installing this skill. Independent of the…
Hook Claude Code
One of 4 in hooks.json
Runs when a session starts on startup, clear and compact, running an inline shell check. From Arcadia-1/analog-agents.
Hook Claude Code
One of 4 in hooks.json
Runs after a tool call finishes for spectre, virtuoso-bridge, Write and Edit tool calls, executing post-sim.sh and post-netlist-check.sh (2 commands). From Arcadia-1/analog-agents.
Hook Claude Code
One of 4 in hooks.json
Runs before the agent uses a tool for Write and Edit tool calls, running an inline shell check. From Arcadia-1/analog-agents.
Hook Claude Code
One of 4 in hooks.json
Runs when the agent finishes a response, executing session-summary.sh. From Arcadia-1/analog-agents.
Skill Claude CodeCodex
ADC characterization orchestrator in the analog-agents project. Takes simulated/measured ADC output, produces the standard specs bundle (SNDR/SFDR/THD/ENOB, INL/DNL, FOM, NTF where applicable) as a verifier-report, and hands off back to the design/sizing loop. TRIGGER when the user asks to characterize an ADC, extract…
Skill Claude CodeCodex
Audit analog circuit netlists for correctness, quality, and risks. Supports both pre-layout (schematic) and post-layout (extracted) netlists. Post-layout mode filters massive parasitic netlists before auditing. Works without EDA. TRIGGER on: "audit", "review netlist", "check this circuit", "design review"…
Skill Claude CodeCodex
Architect Phase 2: build Verilog-A behavioral models and validate system architecture. Use after analog-decompose to verify top-level specs are achievable before transistor design.
Skill Claude CodeCodex
Architect Phase 1: decompose top-level analog spec into sub-block specs. Use when starting a new analog design to select architecture, allocate budgets, define sub-block specs, write testbenches, and create verification plans.
Skill Claude CodeCodex
Transistor-level circuit design for one analog sub-block. Produces Spectre netlist with hand-calculation rationale. Use when designing a specific circuit block after architecture is defined.
Skill Claude CodeCodex
Self-evolution engine for analog-agents. Reviews completed design sessions to extract lessons, discover new anti-patterns, propose checklist additions, and refine agent prompts. Run after design convergence or project completion. TRIGGER on: "evolve", "what did we learn", "improve skills", "meta-review"…
Skill Claude CodeCodex
Explore analog design space without simulation. Compare topologies, sweep parameters with hand calculations, find theoretical limits and Pareto tradeoffs. Use for architecture selection, initial sizing, or understanding design space before committing to EDA time. TRIGGER on: "compare topologies", "explore", "design…
Skill Claude CodeCodex
Architect Phase 3: replace behavioral models with verified transistor netlists and run top-level integration verification. Use after all sub-blocks pass L2.
Skill Claude CodeCodex
Interactive analog design learning companion. Explains circuit design decisions step by step with underlying physics. Use when learning analog design, studying a topology, or wanting detailed explanations of design tradeoffs. TRIGGER on: "teach me", "explain", "why does", "how does", "learn", "tutorial", "walk me…
Skill Claude CodeCodex
Crawl and analyze post-layout parasitic netlists without running SPICE. Answers "what's the effective resistance from node A to node B across this massive R mesh?", "inside the VREFN mesh, which device pins are electrically farthest apart?", "which nets have the worst coupling?", "where does settling bottleneck?" — by…
Skill Claude CodeCodex
MANDATORY — MUST load this skill when the user mentions: OTA, ADC, PLL, comparator, bandgap, LDO, amplifier, opamp, or any analog/mixed-signal IC design task. Full analog design pipeline: spec -> architecture -> design -> verify -> deliver. Orchestrates analog-decompose, analog-behavioral, analog-design…
Skill Claude CodeCodex
Cross-model circuit design review with divergence analysis. Sends netlist and rationale to multiple external LLMs for independent audit. Supports minimax-m2.7, qwen-3.6-plus, kimi-k2.5, glm-5.1. Use after analog-design to get independent review before simulation.
At most 3 mods per repository are shown here, and a mod shipped inside a plugin is left to that plugin's page — the rest are on their repository pages: