Getting it into your agent
One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.
npx skills add Dissipative-ATLAS/jlceda-codex-mcp --skill jlcpcb-headstage-pcbgit clone --depth 1 https://github.com/Dissipative-ATLAS/jlceda-codex-mcpWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/skills/dissipative-atlas/jlceda-codex-mcp/jlcpcb-headstage-pcb)<a href="https://agentmods.dev/skills/dissipative-atlas/jlceda-codex-mcp/jlcpcb-headstage-pcb"><img src="https://agentmods.dev/badge/skills/dissipative-atlas/jlceda-codex-mcp/jlcpcb-headstage-pcb/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/skills/dissipative-atlas/jlceda-codex-mcp/jlcpcb-headstage-pcb"><img src="https://agentmods.dev/badge/skills/dissipative-atlas/jlceda-codex-mcp/jlcpcb-headstage-pcb.svg" alt="Reviewed on agentmods" width="80" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00170 | $0.03234 |
| Opus 5.5 | $0.00068 | $0.01294 |
| Sonnet 5.5 | $0.00034 | $0.00647 |
| Haiku 4.5 | $0.00017 | $0.00323 |
Grade A, and why
jlcpcb-headstage-pcb scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 1mo ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 199 lines — stays where its author put it; the contents beside it link to each section on GitHub.
JLCPCB Headstage PCB
Core Workflow
Use this skill as a project-specific review guide, not as an official JLCPCB fabrication rulebook.
- If the user asks about the existing RHS2116/LFP, 80channel_v2, or power-board project family, read
references/project-lessons.mdandreferences/pcb-rules.mdfirst. - If the user provides a new
.eprj2file, runscripts/extract_eprj2_summary.py <path-to-eprj2>before making design claims, then compare the result with the reference files. - If the user provides a Gerber/CAM export folder,
.DRLdrill files, orFlyingProbeTesting.json, runscripts/summarize_cam_folder.py <path-to-folder>and readreferences/cam-output.md. - If the task is BOM, component choice, JLCPCB/LCSC metadata, SMT assembly, connector choice, BGA/FPC/BTB risk, or footprint risk, read
references/part-library.md. - If the task is parsing or validating
.eprj2internals, readreferences/eprj2-format.md. - If the user asks for current official JLCPCB manufacturing, DFM, or SMT rules, verify against official current sources before treating any number as a manufacturing limit.
Review Priorities
Start reviews in this order:
- Power tree:
BAT,VBUS+5,VCC,VCC_SW,VCC3V3,VCC1V2,VSTM-5,V_WL, regulators/chargers/switches, return paths, and decoupling. - Analog/electrode interface: RHS2116/RHD2164 inputs,
A0throughA63, FE nets, high-impedance routing, local bypassing, quiet ground, and connector or contact-pad pinout sanity. - Digital interfaces:
USB_D+,USB_D-,MISO1,MOSI1,SCK1,CS1,MISO2,MOSI2,SCK2,CS2, FPGA flash nets, line length, layer changes, and nearby ground return. - Stackup and copper planes: distinguish the two-layer LFP/power boards, four-layer 80channel_v2
.eprj2boards, and six-copper-layer quality-test CAM export before applying any layout heuristic. - Manufacturing output: Gerber layer set, board outline, drill tools, flying-probe pin/net coverage, paste/solder mask presence, and top/bottom assembly balance.
- Compact-board manufacturability: 0201/0402 density, BGA escape, FPC/BTB connector pitch, via size, solder-mask expansion, silkscreen clearance, test pads, contact pads, and extended-part dependency.
- Lichuang EDA project integrity: schematic-to-PCB conversion, named nets versus generated nets, BOM flags, LCSC supplier fields, active copper layers, and footprint metadata.
What ships with it
8 files beside SKILL.md in the same directory: the scripts, references and assets a skill reads on demand. Not counted in the per-session cost; read them before you install if any of them is executable.
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 1mo ago First seen · 199 lines · 170 tokens per session scan A 37156cd4397a
jlcpcb-headstage-pcb is a skill published in the GitHub repository Dissipative-ATLAS/jlceda-codex-mcp (4 stars, last pushed 3mo ago), licensed MIT. It adds 170 tokens to every session and 3,234 once invoked, about $0.0007 per session on Opus 5.5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-31.
Other skills, from other repositories
kicad-pcb-review
Use this skill when reviewing, fixing, validating, or preparing KiCad PCB projects with the kicad MCP server.
kicad-pcb-review
KiCad PCB review and manufacturing readiness agent skill for Cursor.
schematic-design
Use when executing a schematic placement plan (plan mode) or modifying an existing schematic (modification mode).
circuit-design
Use when designing an electronic circuit from requirements, choosing topology or regulator type, selecting component values, planning protection circuits, or deciding what goes on a board before schematic capture begins. Also use when the user asks "what components do I need" or "how should I power this.".
pcb-layout
Use when placing footprints on a PCB, routing traces, adding vias or copper zones, deciding trace widths, or planning board layout strategy. Also use when the user asks about PCB stackup, ground planes, trace spacing, or component placement on a board.
verification
Use when running ERC or DRC checks, fixing electrical or design rule violations, debugging unconnected nets, resolving "power pin not driven" errors, or preparing a design for manufacturing export. Also use when the user says "my ERC has errors" or "DRC is failing.".