mapleleavessssssss-wq

mapleleavessssssss-wq/vivado-mcp

Skill Claude CodeCodex

A Vivado workflow for reviewing clock-domain crossing, or CDC, reports in FPGA designs. CDC checks whether signals moving between unrelated clock rates are synchronized and transferred safely.

mapleleavessssssss-wq/vivado-mcp

Skill Claude CodeCodex

A Vivado workflow for writing and reviewing XDC constraints for FPGA clocks, I/O timing, and timing exceptions. XDC is the constraint-file format that tells Vivado about clocks, pins, delays, and allowed timing relationships.

mapleleavessssssss-wq/vivado-mcp

Skill Claude CodeCodex

A workflow for opening or creating Vivado FPGA projects, checking their files and constraints, and reviewing or running hardware builds. Vivado is AMD's software for designing FPGA circuits.

mapleleavessssssss-wq/vivado-mcp

Skill Claude CodeCodex

A Vivado workflow for finding and fixing setup, hold, and pulse-width timing problems in FPGA designs. Timing closure means meeting the required signal timing without changing the design's intended behavior.

mapleleavessssssss-wq/vivado-mcp

Skill Claude CodeCodex

A Vivado waveform-debugging workflow for examining VCD simulation traces, which record signal values over time. It can query selected signals and time ranges without opening a full Vivado session.