Getting it into your agent
It runs from inside its repository, so the clone comes first — what it calls does not travel with the file alone.
git clone --depth 1 https://github.com/vibeic/vibe-icnpx agentmods add skills/vibeic/vibe-ic/hls-c2rtlWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/skills/vibeic/vibe-ic/hls-c2rtl)<a href="https://agentmods.dev/skills/vibeic/vibe-ic/hls-c2rtl"><img src="https://agentmods.dev/badge/skills/vibeic/vibe-ic/hls-c2rtl/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/skills/vibeic/vibe-ic/hls-c2rtl"><img src="https://agentmods.dev/badge/skills/vibeic/vibe-ic/hls-c2rtl.svg" alt="Reviewed on agentmods" width="80" height="20"></a>- NVIDIA SkillSpector pass
What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00079 | $0.01050 |
| Opus 5 | $0.00039 | $0.00525 |
| Sonnet 5 | $0.00016 | $0.00210 |
| Haiku 4.5 | $0.00008 | $0.00105 |
Grade A, and why
hls-c2rtl scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 11d ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 100 lines — stays where its author put it; the contents beside it link to each section on GitHub.
HLS (C/C++ → RTL)
Doctrine (v0.1.50): 把修法寫進工具,而非寫進 prompt. The HLS tool is the source of RTL; AI is the backstop on pragma narrative.
High-Level Synthesis is the entry point for DSP / AI accelerator /
image-processing blocks where the algorithm is already written in
C/C++. This skill guides the lowering from algorithm to RTL with
pragmas / directives and hands off to /rtl-review.
Mandatory Deterministic Preflight
# 1. After HLS emits RTL, the standard plugin gates apply IMMEDIATELY:
python3 plugins/vibe-ic/programs/rtl_review_aggregate.py \
--rtl-dir <hls-output-dir> # see skills/rtl-review for backing
python3 plugins/vibe-ic/programs/rtl_hygiene_lint.py \
<hls-output-dir>/*.v
python3 plugins/vibe-ic/programs/reset_discipline_check.py \
--rtl-dir <hls-output-dir>
HLS-emitted RTL is NOT exempt from plugin gates — many HLS tools emit RTL with subtle latch / reset-discipline issues that downstream synthesis catches only after wasted hours. Refuse to claim "HLS RTL is correct" without running the same gates a hand-authored RTL would face.
When to use
- Algorithmic block (filter, matrix multiply, feature extractor) exists in C/C++/SystemC
- Dataflow-heavy pipeline where manual RTL would be error-prone
- Design-space exploration across latency vs throughput vs area
- Target flow: Vitis HLS, Catapult HLS, Stratus HLS, XLS (open source, Google)
Inputs
- Source file(s) — C/C++/SystemC
- Test vectors (golden I/O pairs)
- Target: FPGA (bitstream) vs ASIC (Verilog netlist)
- Constraints: target clock period, latency budget, throughput, resource limits
- Tool choice
Workflow
- Clean the source: remove pointer chasing, dynamic allocation, recursion — HLS only digests statically-bounded C
- Interface synthesis: decide on AXI-Stream, AXI-Lite, memory-mapped BRAM, or wire handshake for each argument
- Apply pragmas / directives:
#pragma HLS PIPELINE II=1for loops#pragma HLS UNROLL factor=N#pragma HLS DATAFLOWfor stream pipelines#pragma HLS ARRAY_PARTITIONfor memory banks
- Co-simulate C vs generated RTL using the test vectors
- Emit RTL and hand off to
/rtl-reviewand/testbench-gen - Report PPA — estimated from HLS tool's synthesis report
What ships with it
2 files beside SKILL.md in the same directory: the scripts, references and assets a skill reads on demand. Not counted in the per-session cost; read them before you install if any of them is executable.
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 11d ago First seen · 100 lines · 79 tokens per session scan A 06c0494e484d
hls-c2rtl is a skill published in the GitHub repository vibeic/vibe-ic (23 stars, last pushed today), licensed Apache-2.0. It adds 79 tokens to every session and 1,050 once invoked, about $0.0004 per session on Opus 5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-30.
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