cortex-m-patterns

cortex-m-patterns

Knowledge Base

Real ARM Cortex-M patterns used in production firmware. All code targets C11 with arm-none-eabi-gcc unless noted.

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Pattern 1: SysTick Configuration

SysTick is a 24-bit down-counter built into every Cortex-M. Used as the RTOS tick source or a simple 1ms timebase.

/* Configure SysTick for 1ms interrupt at SystemCoreClock = 168 MHz */
/* Returns 0 on success, 1 if reload value exceeds 24-bit counter   */
uint32_t systick_init_1ms(void)
{
    return SysTick_Config(SystemCoreClock / 1000U);
    /* SysTick_Config: sets LOAD = (ticks-1), CTRL = CLKSOURCE|TICKINT|ENABLE */
}

volatile uint32_t g_tick_ms = 0;

void SysTick_Handler(void)
{
    g_tick_ms++;
}

uint32_t get_tick_ms(void)
{
    return g_tick_ms;
}

void delay_ms(uint32_t ms)
{
    uint32_t start = get_tick_ms();
    while ((get_tick_ms() - start) < ms) { __NOP(); }
}

Key: SysTick_Config is CMSIS-Core, defined in core_cm4.h. The RELOAD value is (SystemCoreClock/ticks_per_sec) - 1.

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Pattern 2: NVIC Priority Grouping

Priority grouping splits the 8-bit priority register into preempt bits and sub-priority bits.

/* NVIC_PRIORITYGROUP_4: 4 bits preempt (0-15), 0 bits sub.
   NVIC_PRIORITYGROUP_2: 2 bits preempt (0-3),  2 bits sub. */

/* STM32 HAL sets NVIC_PRIORITYGROUP_4 in HAL_Init() */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);

/* DMA stream2 at preempt=5, sub=0 */
HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn);

/* UART1 at lower preempt than DMA so DMA can preempt UART ISR */
HAL_NVIC_SetPriority(USART1_IRQn, 6, 0);
HAL_NVIC_EnableIRQ(USART1_IRQn);

Rule: FreeRTOS requires all ISRs that call FromISR API to have priority numerically >= configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY (lower urgency). Hardware-only ISRs (DMA completion triggering semaphore) can use any priority.

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Pattern 3: Cortex-M4 FPU Enable

Must execute before any floating-point instruction, before FreeRTOS scheduler starts.