Open Agentic Design Automation - The open agent interface for EDA: Agent–EDA Contract
Skill Claude CodeCodex
Analyze feedback-loop stability with backend-independent OpenADA evidence. Use for differential, common-mode, nested, feed-forward, regulator, or switched-loop questions involving operating-point validity, loop injection and probe identity, gain and phase crossover review, phase or gain margin, closed-loop…
Skill Claude CodeCodex
Analyze waveform spectra and linearity with backend-independent OpenADA evidence. Use for FFT setup, coherent sampling, windowing, alias folding, SFDR, harmonic distortion, HD2 or HD3, sampled-data spurs, before/after linearity comparisons, or diagnosing an untrustworthy spectral scalar while preserving exact…
Skill Claude CodeCodex
Assess synthesis-stage ASIC setup and hold timing with backend-independent OpenADA evidence. Use when validating a mapped netlist against a Liberty corner and SDC, reviewing WNS, TNS, unconstrained endpoints and worst setup/hold path summaries, diagnosing whether a timing miss is trustworthy, comparing one controlled…
Skill Claude CodeCodex
Plan and assess deterministic PVT, sweep, mismatch, and Monte Carlo campaigns through composable OpenADA intents. Use when expanding explicit corner matrices, checking specifications across process-voltage-temperature or load conditions, accounting for pass/fail/unknown points, computing bounded raw-yield summaries…
Skill Claude CodeCodex
Assess ASIC synthesis, technology mapping, and inferred hardware with backend-independent OpenADA evidence. Use when reviewing whether RTL produced a complete Liberty-mapped netlist, investigating unexpected register, latch, memory, arithmetic, or mux structures, comparing controlled synthesis experiments, or deciding…
Skill Claude CodeCodex
Bootstrap and coordinate a fresh open-source ASIC project when the PDK, EDA runtime, project configuration, or physical-design collateral is missing or ambiguous. Use for requests to choose an open PDK, provision compatible tools, create a reproducible ASIC workspace, turn RTL such as a CPU into a core or full-chip…
Skill Claude CodeCodex
Analyze, plan, and review backend-independent analog-block behavior and characterization through OpenADA semantic intents. Use for qualitative schematic or topology reasoning, transient-phase and scaling analysis, device-sizing tradeoffs, defining a characterization matrix for an amplifier, regulator, comparator…
Skill Claude CodeCodex
Close analog, mixed-signal, custom-digital, or top-level IC layout through small visually reviewed increments with fresh DRC, LVS, extraction, and performance evidence. Use when editing or debugging GDS, OASIS, Magic, KLayout, or custom-cell layout; placing matched or parasitic-critical devices; routing sensitive…
Skill Claude CodeCodex
Discover, invoke, and interpret open-source EDA tools through OpenADA's versioned CLI contract. Use for semiconductor or electronics work involving Xschem schematics (.sch), SPICE simulation, GDS/KLayout DRC, Netgen LVS, Verilog/SystemVerilog lint, Yosys ASIC synthesis, OpenSTA timing, PDK discovery, or diagnosing an…
Skill Claude CodeCodex
Review circuit-simulation evidence and recommend the next engineering action through OpenADA's backend-independent circuit.simulate contract. Use when assessing a SPICE operating-point, DC, AC, or transient run; deciding whether simulation evidence is trustworthy; comparing normalized evidence across supported…
Skill Claude CodeCodex
Review ASIC RTL architecture with backend-independent OpenADA lint and structural evidence. Use for SystemVerilog or Verilog design reviews involving hierarchy, clocks and resets, state/control structure, parameterization, inferred latches or combinational loops, arithmetic width, signedness, overflow or saturation…