assess-asic-timing

Assess ASIC Timing

Evaluate one constraint-bound mapped-netlist timing model and recommend one evidence-backed closure experiment. Use $openada:openada for execution and normalized results. Keep native command construction and report parsing below the semantic boundary.

Scope the claim before running

Use exactly:

• openada.operation/timing.analyze/v1alpha1
• openada.assertion/timing.constraints-satisfied/v1alpha1
• openada.feature/timing.setup-hold/v1alpha1

The v1alpha1 operation is synthesis-stage static timing for one mapped netlist, one Liberty, one SDC, one top, and ideal interconnect. It can establish whether its complete declared setup/hold timing model has nonnegative slack. It does not establish routed parasitics, extraction, slew/capacitance integrity, clock-tree behavior, crosstalk/noise, IR drop, electromigration, OCV/AOCV/POCV, MCMM coverage, asynchronous correctness, false/multicycle-path intent, or foundry signoff.

When reviewing routed evidence produced outside this v1alpha1 operation, distinguish a tool's raw report_parasitic_annotation -report_unannotated driver count from a layout-aware filtered count. Ports, logical pad terminals, and synthetic loads can be reported as unannotated even when their database nets have no physical wire and therefore no routed RC to extract. Require the exact reported identities and the flow's documented wire-presence filter. A nonzero raw count with zero physically wired unannotated nets is not evidence of missing routed parasitics; a physically wired unannotated net remains an unknown timing-coverage gap.

Freeze the timing manifest

Record:

• passing synthesis result-envelope path plus exact mapped-netlist path, byte count and hash;
• exact Liberty path/hash, PVT corner, units, operating condition, and library provenance;
• exact SDC path/hash and the source/owner of every clock, generated clock, IO delay, uncertainty, latency, transition, load, exception, and case analysis;
• top, analysis stage, ideal-interconnect limitation, and intended clock/path relationships;
• selected operation/feature, implementation and native product/version, evidence directory, result-envelope path, and expected artifact roles;
• explicit project acceptance criteria beyond zero slack, if any.