close-layout-incrementally

Close Layout Incrementally

Treat visual inspection as a required diagnostic loop and tool-native evidence as the engineering gate. Use $openada:openada for capability discovery, DRC, LVS, simulation, and normalized result interpretation. Keep the selected PDK, rule deck, extraction setup, schematic, models, and native layout authoritative.

Freeze one closure context

Record before editing:

• writable layout and immutable baseline hashes;
• exact cell and hierarchy boundary under review;
• authoritative PDK revision, layer map, DRC deck, LVS setup, extraction setup, models, schematic/netlist, and simulator startup chain;
• device intent, net intent, matching or symmetry constraints, current paths, sensitive nodes, and supplied DRC/LVS/parasitic/performance limits;
• known-good DRC, LVS, PEX, and simulation evidence for the baseline.

Do not mix collateral revisions to obtain a pass. If the authoritative process context is ambiguous, stop before changing geometry and request that choice.

Choose the smallest meaningful increment

Change one independently reviewable unit:

• one device or matched device pair;
• one contact or via array;
• one local route or critical-net segment;
• one guard-ring, well, tap, shield, or power connection;
• one block-boundary pin or one hard-macro integration edge.

Do not place or connect the whole block at once. Preserve the prior passing checkpoint. State the expected connectivity and parasitic effect before the edit, including the planned route and return path.

For matched or high-frequency structures, begin with the minimum meaningful pair. Close that pair before adding bias, load, cascode, common-mode, or routing structures. Repeat the same rule when joining completed blocks: connect one interface or critical net, then reclose the hierarchy.

Render before and after every edit

Produce all views needed to understand the increment:

1. full-cell context with hierarchy visible;
2. marker-centered zoom with coordinates and scale;
3. isolated device, cut, and adjacent conductor layers;
4. connectivity context one level above and below the edited cell;
5. before/after views at the same crop, layer visibility, and resolution.