Skill Claude CodeCodex
Execute hardware measurements on analog blocks via scope capture + FPGA ADC read. Use when running hardware-in-the-loop verification, "measure analog", "scope capture", "read ADC", or during analog hardware tuning.
Skill Claude CodeCodex
Generate FPGA RTL for hardware-in-the-loop analog testing — digital stimulus controller + ADC readback + scope trigger. Use when verifying analog blocks on real hardware, "generate hw testbench", "FPGA analog test", or at the hardware verification phase.
Skill Claude CodeCodex
Closed-loop hardware-in-the-loop analog tuning — iterates SPICE sizing → hardware build → measure → compare → adjust until hardware matches SPICE matches spec. Use when the user says "tune analog on hardware", "hardware convergence", "HIL tuning loop".
Skill Claude CodeCodex
Plan analog layout with matching, common-centroid, interdigitation, dummy devices, guard rings, and shielding. Use when the user says "analog layout", "matching layout", "common centroid", "dummies", "guard ring", "interdigitated", "current mirror layout", "differential pair layout".
Skill Claude CodeCodex
Generate a complete SPICE netlist (.sp) from a sized analog topology, with correct PDK device models, body connections, and testbench. Use when the user says "generate SPICE", "write netlist", "create spice deck", or at Step A3 of the analog track.
Skill Claude CodeCodex
After analogoneshotrunner emits A1..A9 outputs, AI spot-checks corner-sim coverage, hardmacro completeness, HIL data fidelity. Triggers on /vibe-ic-analog PASS or phrases like "review analog", "verify A8 hardmacro", "check analog corners".
Skill Claude CodeCodex
Closed-loop analog optimization — iterates sizing → netlist → SPICE corner sweep → spec check → re-size until all PVT corners pass. Use when the user says "optimize the analog block", "close the loop", "auto-size", or at Step A4 of the analog track.
Skill Claude CodeCodex
Size transistors in an analog circuit topology to meet performance specs (gain, bandwidth, noise, power). Use when the user says "size this amplifier", "analog sizing", "op-amp design", "bias point", "find W/L", or shares a schematic and a spec table.
Skill Claude CodeCodex
Extract analog block specifications from L1/L5 design documents into machine-readable spec.json per block. Use when starting the analog design track, or when the user says "extract analog specs", "what analog blocks do we need", "analog block list".
Skill Claude CodeCodex
Select circuit topology for each analog block based on specs and PDK constraints. Use when the user says "what topology for the LDO", "analog topology", "circuit architecture", or at Step A2 of the analog track.
Skill Claude CodeCodex
Explore micro-architecture trade-offs (pipeline depth, parallelism, memory hierarchy, bus width) against PPA targets before committing to RTL. Use when the user says "architecture exploration", "design space exploration", "DSE", "pipeline depth", "parallelism", "micro-architecture", "trade-off study".
Skill Claude CodeCodex
MANDATORY after ANY close-loop or real-case run where AI judgment recovered a previously-failing case — not just RTL authoring. Applies to EVERY step in the Vibe-IC flow: Phase 1 NL ingestion, Phase 2 spec-to-RTL / chiptop / synth / TB / rtlrepairretry / lint / conformance / audit, Phase 3 synth / PnR / CTS / DRC /…
Skill Claude CodeCodex
Normalized, MANDATORY end-to-end verification for any benchmark IC after it has been driven from Design Documents → generated RTL → silicon through the full Vibe-IC flow. Produces ONE BENCHMARKVERIFICATIONREPORT.md per IC covering all six pillars with hard gates: (1) Functional Verification Coverage == 100%…
Skill Claude CodeCodex
When designoneshotrunner.steprtlgen WAIVES rtlgen and ipcatalogquery has emitted matches, this skill pulls the matched open-source IP RTL into the project's canonical phase2/stage1/rtl/ directory and authors only the integration wrapper / chip-top + OpenLane config glue from L1-L27 spec. Replaces full-from-scratch…
Skill Claude CodeCodex
Verify that all required artifacts exist and pass quality checks before advancing to the next phase. Triggers at Phase 1→2 and Phase 2→3 transitions. Use when: 'ready to proceed', 'check if we can move on', 'checkpoint', 'sign off', or at the end of each phase. This is a MANDATORY gate — no phase transition without…
Skill Claude CodeCodex
Record a general (IC-agnostic) backlog item from the current design session. Use when the agent encounters a bug, issue, or enhancement opportunity in the plugin or MCP tools. Invoke at any point during Phase 1/2/3 when you discover a gap.
Skill Claude CodeCodex
After flowcompliancecheck.py reports Overall=PASS, AI spot-checks a sample of gates for false-PASS / gameable patterns. Triggers automatically when /vibe-ic-phase2/3/23/all returns PASS, before claiming tapeout-ready.
Skill Claude CodeCodex
Closed-loop core-agent that fixes plugin issues filed by the field-agent. Invoke as a cron prompt; the loop polls the repo for ANY OPEN non-PR issue (new OR reopened — no label gating, no comment classifier), reproduces and fixes the bug chip-AGNOSTIC-ally, SELF-VERIFIES (reproduce + run the cadence-correct plugin…
Skill Claude CodeCodex
Design-for-ECO methodology — pre-place a distributed pool of tied-off spare standard cells/gates and reserve spare ECO pads so that a late-stage bug can be fixed with a cheap metal-only ECO instead of a full base-layer respin. Covers WHY (metal-only vs base-layer respin cost), WHAT to insert…
Skill Claude CodeCodex
Diagnose and fix Design Rule Check (DRC) violations in a layout or GDS. Use when the user says "fix DRC", "DRC clean", "resolve spacing errors", "my layout fails DRC", or shares a DRC report from Calibre, Klayout, or Magic.
Skill Claude CodeCodex
Plan an Engineering Change Order (ECO) — a late-stage design change that minimizes disruption to an already-placed-and-routed netlist. Use when the user says "need an ECO", "late-stage fix", "spin without re-place-and-route", "metal-only fix", or describes a bug found after P&R.
Skill Claude CodeCodex
Run Logic Equivalence Checking (LEC) between two representations of a design — RTL vs gate-level netlist, pre-ECO vs post-ECO, or golden vs revised RTL — to prove functional identity. Use when the user says "LEC", "equivalence check", "formal equivalence", "is this netlist equivalent", "post-ECO check".
Skill Claude CodeCodex
Closed-loop field-agent that drives plugin quality improvements by running phase1/phase2/phase3 on benchmark IC projects, DRILLING each systematic gap to a fully-converged all-layers-resolved state in its OWN sandbox worktree, then handing the gatekeeper ONE complete verified bundle (candidate.patch + per-layer…
Skill Claude CodeCodex
MANDATORY before landing any change to the FLOW itself — a gate, a check, a step, a phase runner, a verdict rule, or anything under programs/ that every design passes through. Flow-level changes are foundational: when they are right every cell benefits, and when they are wrong every cell lies at once and nobody…