Getting it into your agent
It runs from inside its repository, so the clone comes first — what it calls does not travel with the file alone.
git clone --depth 1 https://github.com/vibeic/vibe-icnpx agentmods add skills/vibeic/vibe-ic/analog-layoutWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/skills/vibeic/vibe-ic/analog-layout)<a href="https://agentmods.dev/skills/vibeic/vibe-ic/analog-layout"><img src="https://agentmods.dev/badge/skills/vibeic/vibe-ic/analog-layout/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/skills/vibeic/vibe-ic/analog-layout"><img src="https://agentmods.dev/badge/skills/vibeic/vibe-ic/analog-layout.svg" alt="Reviewed on agentmods" width="80" height="20"></a>- NVIDIA SkillSpector pass
What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00068 | $0.06068 |
| Opus 5 | $0.00034 | $0.03034 |
| Sonnet 5 | $0.00014 | $0.01214 |
| Haiku 4.5 | $0.00007 | $0.00607 |
Grade A, and why
analog-layout scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 6d ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 393 lines — stays where its author put it; the contents beside it link to each section on GitHub.
Analog Layout
analog-sizing picks W/L; this skill translates the sized schematic into a layout plan that actually survives process variation. Matching and noise immunity live or die on layout, not schematic.
When to use
- Current mirrors, differential pairs, bandgap references, DAC ladders
- Any circuit where σ(Vth) or σ(β) matching drives the spec
- Circuits near digital noise sources (guard rings / shielding needed)
- Before handing off to a layout engineer or Magic / Virtuoso
Inputs
- Sized schematic with device list (W, L, M, NF)
- Matching pairs / groups (which devices must match)
- Sensitivity list (which mismatches kill which spec)
- PDK rules (well spacing, latch-up, antenna)
- Floorplan block size budget
Workflow
- Identify matching groups — pairs, quads, ratios
- Choose matching style:
- Common-centroid 2×2, 4×4 for differential pairs
- Interdigitation ABAB or ABBA for current mirrors
- Centroid-preserving patterns for large ratios
- Dummy devices: at least 2 dummies on each side of a matching row
- Guard rings: n-well ring around PMOS, p-substrate ring around NMOS near digital
- Routing rules:
- Symmetric routing for differential signals
- Shielded routing for sensitive nodes (clock, bandgap output)
- Avoid crossing a matched row with unrelated metal
- Density / antenna: ensure fill rules and antenna rules met without breaking symmetry
- Post-layout extraction: plan for RC back-annotation → re-simulate → may need sizing iteration
Drawing a layout that actually closes A6 (measured recipe)
Everything above produces a plan. A6 (analog_a6_block_pv_check) does not grade plans: it
demands DRC == 0 AND a netgen LVS match, per block. eda_analog_layout cannot supply that —
it is honest that it returns status: SCAFFOLD because readspice + gds write places nothing.
So the layout is authored here, and three separate things have to be true. Each line below was
measured on sky130A (magic 8.3.679, device generator 1.0.599); the shape of the rule is
PDK-independent, the numbers are not.
What ships with it
2 files beside SKILL.md in the same directory: the scripts, references and assets a skill reads on demand. Not counted in the per-session cost; read them before you install if any of them is executable.
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 6d ago Changed · +101 lines 7ce16c06ec5a
- 10d ago First seen · 292 lines · 68 tokens per session scan A 65edf53edee0
analog-layout is a skill published in the GitHub repository vibeic/vibe-ic (23 stars, last pushed today), licensed Apache-2.0. It adds 68 tokens to every session and 6,068 once invoked, about $0.0003 per session on Opus 5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-30.
Other skills, from other repositories
analog-netlist-crawl
Crawl and analyze post-layout parasitic netlists without running SPICE. Answers "what's the effective resistance from node A to node B across this massive R mesh?", "inside the VREFN mesh, which device pins are electrically farthest apart?", "which nets have the worst coupling?", "where does settling bottleneck?" — by…
analog-design
Transistor-level circuit design for one analog sub-block. Produces Spectre netlist with hand-calculation rationale. Use when designing a specific circuit block after architecture is defined.
analog-verify
Pre-simulation review and Spectre simulation verification for analog circuits. Reviews circuit netlist and testbench, runs simulation, produces margin report. Use after analog-design completes a netlist.
analog-pipeline
MANDATORY — MUST load this skill when the user mentions: OTA, ADC, PLL, comparator, bandgap, LDO, amplifier, opamp, or any analog/mixed-signal IC design task. Full analog design pipeline: spec -> architecture -> design -> verify -> deliver. Orchestrates analog-decompose, analog-behavioral, analog-design…
analog-audit
Audit analog circuit netlists for correctness, quality, and risks. Supports both pre-layout (schematic) and post-layout (extracted) netlists. Post-layout mode filters massive parasitic netlists before auditing. Works without EDA. TRIGGER on: "audit", "review netlist", "check this circuit", "design review"…
analog-decompose
Architect Phase 1: decompose top-level analog spec into sub-block specs. Use when starting a new analog design to select architecture, allocate budgets, define sub-block specs, write testbenches, and create verification plans.