Claude Code skills for hardware design, validation, and bring-up
Agent
Use this agent when bare-metal code, firmware, or an FPGA design will not come up on real hardware: it boots but hangs, faults early, gives no output, or configuration silently fails. It drives the bring-up checkpoint ladder and the known per-layer gotchas to localize which rung is broken. Dispatch it for "boots in…
Agent
Use this agent to review HDL/RTL changes (ROHD, Chisel, SpinalHDL, Verilog, VHDL) before merge or tapeout. It reviews a diff or a set of modules against hardware design red flags: parameterization and validation, ROHD simulation pitfalls, area/timing structure, address-map integrity, and silicon-grade discipline.…
Agent
Use this agent before a tapeout or MPW shuttle submission to run the precheck gate and decide whether the design is genuinely ready. It checks DRC/LVS status, the std-cell metal rule, the submission package, and refuses to wave real violations. Dispatch it when someone is about to send a GDS to a foundry or shuttle.