Plugin Claude Code
Hardware design, bring-up, verification, and tapeout skills for Claude Code.
Plugin Claude Code
Hardware design, bring-up, verification, and tapeout skills for Claude Code.
Plugin Claude Code
Skills for hardware design, bring-up, verification, and tapeout: HDL modules, SoC integration, FPGA and bare-metal bring-up, differential verification, codegen validation, tapeout precheck, and Nix EDA packaging.
Agent
Use this agent when bare-metal code, firmware, or an FPGA design will not come up on real hardware: it boots but hangs, faults early, gives no output, or configuration silently fails. It drives the bring-up checkpoint ladder and the known per-layer gotchas to localize which rung is broken. Dispatch it for "boots in…
Agent
Use this agent to review HDL/RTL changes (ROHD, Chisel, SpinalHDL, Verilog, VHDL) before merge or tapeout. It reviews a diff or a set of modules against hardware design red flags: parameterization and validation, ROHD simulation pitfalls, area/timing structure, address-map integrity, and silicon-grade discipline.…
Agent
Use this agent before a tapeout or MPW shuttle submission to run the precheck gate and decide whether the design is genuinely ready. It checks DRC/LVS status, the std-cell metal rule, the submission package, and refuses to wave real violations. Dispatch it when someone is about to send a GDS to a foundry or shuttle.
Command
Drive the measure-don't-guess FPGA fit and timing loop on a design.
Command
Drive the hardware bring-up checkpoint ladder when something won't come up.
Command
Run the tapeout precheck gate on a design before submission.
Hook
Runs after a tool call finishes for Write, Edit and MultiEdit tool calls, executing check-style.sh via sh. From Midstall/claude-for-hardware.
Skill Claude CodeCodex
Use when bringing up bare-metal or kernel code on a new architecture, SoC, or board (RISC-V, ARM, x86, ESP32) and it won't boot, hangs after boot, or faults early; covers trap vectors, MMU/PMP, syscall ABI, and boot ordering.
Skill Claude CodeCodex
Use when building or debugging a compiler backend, codegen, or assembler and you need to prove the generated machine code is correct by executing it on a real CPU or a fast emulator, not just inspecting the output.
Skill Claude CodeCodex
Use when verifying a hardware DUT (a CPU core, FPGA, or netlist) against a golden reference model, building coverage-guided fuzzing, or detecting where silicon diverges from a simulator like Spike, an emulator, or SPICE.
Skill Claude CodeCodex
Use when building or debugging a firmware and boot chain (RISC-V SBI, UEFI, ACPI, a bootloader handoff like Limine to an OS) or adding measured boot with a TPM, and a stage fails to hand off to the next.
Skill Claude CodeCodex
Use when loading a bitstream onto a physical FPGA and driving or observing it over JTAG or GPIO, especially bit-banged JTAG from a host like a Raspberry Pi, or when configuration silently fails.
Skill Claude CodeCodex
Use when synthesizing RTL to an FPGA with yosys/nextpnr (ECP5/Lattice and similar), fighting area or routing congestion, measuring Fmax, deciding why a design won't fit or route, or instantiating block RAM; covers the pre-pack vs post-pack metric trap.
Skill Claude CodeCodex
Use when writing, refactoring, or deciding how to test an HDL module, component, or IP block (ROHD, Chisel, SpinalHDL, Verilog, VHDL) and you need it parameterized, validated, and covered by exhaustive tests rather than a one-off.
Skill Claude CodeCodex
Use when packaging EDA or hardware toolchains in Nix (Yosys, OpenROAD, simulators, vendor tools) and hitting dlopen/plugin/runtime-path failures, or writing derivations and build phases for hardware tooling on aarch64-linux.
Skill Claude CodeCodex
Use when implementing a hardware block, protocol, peripheral, or ISA feature in ROHD and you should ground it in the authoritative spec, existing reference implementations, and reusable libraries you fetch first, instead of writing it from memory.
Skill Claude CodeCodex
Use when building or testing RTL in ROHD (Dart), rohdbridge, or rohdhcl and hitting hierarchy-violation errors, "Bad state: No element" at sim setup, co-simulation failures, SystemVerilog emission name mismatches, or unexpected register read latency.
Skill Claude CodeCodex
Use when optimizing RTL microarchitecture for area or clock frequency (Fmax), a design is too big to fit or too slow to meet timing, a wide multiply or barrel shifter is the critical path, or a "compute everything and select" datapath is too large.
Skill Claude CodeCodex
Use when writing hardware, firmware, verification, or tooling code that will reach real silicon, and you face a tradeoff between shipping fast and shipping correct; covers failures-should-fail, no over-engineering, no-panic, and test coverage.
Skill Claude CodeCodex
Use when composing an SoC from peripherals and a bus fabric, or when generating device trees, ACPI tables, docs, or pin lists from a hardware description and they keep drifting out of sync.
Skill Claude CodeCodex
Use when preparing a design for tapeout or an MPW shuttle submission (wafer.space style), running DRC/LVS signoff, packaging the GDS, or deciding whether a physical-verification failure is safe to wave; covers metal-layer and std-cell rules.