hdl-tools/analog-chip-design-agents
Agent
Orchestrates analog/RF EDA tool detection, output-filtering wrapper deployment, and MCP server configuration. Invoke when setting up an analog design environment, verifying tool availability before a domain orchestrator, or generating per-tool install scripts with TCL modulefiles for a new workstation.
hdl-tools/analog-chip-design-agents
Skill Claude CodeCodex
EDA tool detection, wrapper deployment, and MCP configuration for analog/mixed-signal + RF design environments. Use when setting up a workstation, verifying tool availability before a domain flow, or generating per-tool install scripts with TCL modulefiles.
hdl-tools/analog-chip-design-agents
Skill Claude CodeCodex
Distil append-only experiences.jsonl run records into per-domain knowledge.md summaries for the analog design agents. Use after enough runs accumulate to merge new convergence fixes, sizing recipes, PDK quirks, and tool flags into the Tier-2 knowledge file.
hdl-tools/analog-chip-design-agents
Plugin Claude Code
Analog custom layout — floorplan, matched device generation, symmetry/shielded place and route.
hdl-tools/analog-chip-design-agents
Agent
Orchestrates custom analog layout — floorplan, matched-device generation, symmetric placement, shielded routing, finishing, and a pre-DRC check. Invoke to lay out a block from a signed-off schematic, or to service a fixrequest that repairs the layout after a DRC/LVS or parasitic-degradation failure.
hdl-tools/analog-chip-design-agents
Skill Claude CodeCodex
Floorplan, generate matched devices, and place/route analog blocks with symmetry, shielding, and matching constraints to a clean, DRC-ready layout. Use when turning a sign-off-ready schematic into a GDS layout, or servicing a fixrequest that repairs the layout after a DRC/LVS or parasitic-degradation failure.
hdl-tools/analog-chip-design-agents
Plugin Claude Code
Cross-domain pipeline orchestrator — designstate.json fixrequest loop with iteration cap and checkpoints.
hdl-tools/analog-chip-design-agents
Agent
Drives the closed-loop spec↔circuit↔layout feedback cycle for analog/mixed-signal design. Detects open fixrequests in designstate.json, dispatches the servicer named by each request's routeto hint (circuit-design by default, or behavioral-modeling, custom-layout, em-modeling) then re-validation, enforces the…
hdl-tools/analog-chip-design-agents
Skill Claude CodeCodex
Cross-domain loop orchestration for the analog/mixed-signal + RF design pipeline. Provides the fixrequest protocol, iteration-cap logic, the authoritative designstate.json constraints schema, failure classification, and approval checkpoints. Use when driving the closed-loop spec↔circuit↔layout feedback cycle.
hdl-tools/analog-chip-design-agents
Plugin Claude Code
Verilog-A/AMS, VHDL-AMS and SystemVerilog real-number modeling, OSDI compilation, connect modules.
hdl-tools/analog-chip-design-agents
Agent
Orchestrates Behavioral / AMS Modeling — model planning, Verilog-A authoring, OpenVAF/OSDI compilation, connect-rule setup, and model-vs-SPICE validation, ending in model sign-off. Invoke to build an analog behavioral model, or to service a fixrequest that re-tunes a model after an AMS-verification mismatch.
hdl-tools/analog-chip-design-agents
Skill Claude CodeCodex
Author, compile, and validate analog behavioral models — Verilog-A, Verilog-AMS, VHDL-AMS, and SystemVerilog real-number models — plus the connect modules that bridge analog and digital domains. This is the analog-HDL core of the marketplace. Use when building a fast, accurate model of an analog block for AMS…
hdl-tools/analog-chip-design-agents
Plugin Claude Code
DRC, LVS, antenna/ERC and density/DFM sign-off against foundry decks.
hdl-tools/analog-chip-design-agents
Agent
Orchestrates physical verification — DRC, LVS, antenna/ERC, and density/DFM — ending in a physically-clean sign-off. Invoke to verify a custom layout against the foundry decks and the source netlist, or to re-validate after a custom-layout fixrequest was serviced. Opens fixrequests routed to custom-layout on DRC/LVS…
hdl-tools/analog-chip-design-agents
Skill Claude CodeCodex
Run DRC, LVS, antenna/ERC, and density/DFM checks on an analog layout and sign off a physically-clean GDS. Use when verifying a custom layout against the foundry rule deck and the source netlist, or re-validating after a custom-layout fixrequest was serviced. Opens fixrequests routed to custom-layout on DRC/LVS…
hdl-tools/analog-chip-design-agents
Plugin Claude Code
Post-PEX corner and Monte-Carlo simulation, spec re-verification, and tape-out gating.
hdl-tools/analog-chip-design-agents
Agent
Orchestrates post-layout sign-off — PEX-netlist assembly, post-layout corner/MC simulation, spec re-verification, margin analysis, and the tape-out gate. Invoke to close a block's specs on the extracted netlist, or to re-validate after a fixrequest was serviced. Opens fixrequests routed to custom-layout or…
hdl-tools/analog-chip-design-agents
Skill Claude CodeCodex
Run post-PEX corner and Monte-Carlo simulation on the extracted netlist, re-verify specs against the pre-layout design, and gate tape-out. Use when closing a block's specs on the extracted netlist, quantifying parasitic degradation, or driving the tape-out approval gate. Opens fixrequests routed to custom-layout or…
hdl-tools/analog-chip-design-agents
Plugin Claude Code
Electromigration, IR-drop, ESD, latch-up and aging (HCI/NBTI) analysis and sign-off.
hdl-tools/analog-chip-design-agents
Agent
Orchestrates the reliability flow — EM, IR-drop, ESD, latch-up, and aging (HCI/NBTI) — ending in a long-term-reliability sign-off. Invoke to verify a signed-off, extracted analog block against current/voltage/lifetime limits, or to re-validate after a custom-layout / circuit-design fixrequest was serviced. Opens…
hdl-tools/analog-chip-design-agents
Skill Claude CodeCodex
Run electromigration, IR-drop, ESD, latch-up, and aging (HCI/NBTI) analyses on a signed-off analog layout and sign off long-term reliability. Use when verifying that power/signal routing and devices survive the rated current, voltage, and lifetime, or re-validating after a custom-layout / circuit-design fixrequest was…
hdl-tools/analog-chip-design-agents
Plugin Claude Code
RF/mmWave design — S-parameter, harmonic balance, Pnoise/PAC, IP3 and load-pull.
hdl-tools/analog-chip-design-agents
Agent
Orchestrates the RF/mmWave design flow (rfspec → topologymatching → sparameteranalysis → harmonicbalance → noiselinearity → loadpulloptimization → rfsignoff), signing off an LNA/mixer/VCO/PLL/PA block against the RF spec table across corners. Invoke to run the full RF flow or any individual stage, or to re-validate…
hdl-tools/analog-chip-design-agents
Skill Claude CodeCodex
Design and verify an RF/mmWave block (LNA, mixer, VCO, PLL, PA): topology selection and matching, S-parameter, harmonic-balance, Pnoise/PAC, IP3, and load-pull analyses, signed off against the RF spec table across corners. Use when designing or re-running an RF block. Loop-backs are stage-local first (spec/stability →…