hdl-tools/analog-chip-design-agents
Plugin Claude Code
Plugin marketplace listing 16 plugins: analog-design-architecture, analog-design-modeling, analog-design-circuit, analog-design-simulation, analog-design-ams-verification.
hdl-tools/analog-chip-design-agents
Instructions file GitHub Copilot
Instructions for hdl-tools/analog-chip-design-agents, covering analog chip design — copilot workspace instructions, behaviour for all domains and domain-specific rules.
hdl-tools/analog-chip-design-agents
Plugin Claude Code
Mixed-signal top assembly, boundary/connect rules, chip-level AMS sim and power intent.
hdl-tools/analog-chip-design-agents
Agent
Orchestrates mixed-signal top integration — IP qualification, top assembly, boundary/connect rules, chip-level AMS simulation, power-intent check, and integration sign-off. Invoke to assemble and close a mixed-signal top, or to re-validate after a fixrequest was serviced. Opens fixrequests routed to custom-layout…
hdl-tools/analog-chip-design-agents
Skill Claude CodeCodex
Qualify analog IP, assemble the mixed-signal top, define boundary/connect rules, run chip-level AMS simulation, and check power intent through integration sign-off. Use when integrating signed-off analog/RF blocks into a mixed-signal top, or re-validating after an integration fix. Opens fixrequests routed to…
hdl-tools/analog-chip-design-agents
Plugin Claude Code
Mixed-signal co-simulation, connect rules, RNM regression, and coverage closure.
hdl-tools/analog-chip-design-agents
Agent
Orchestrates AMS verification — mixed-signal testbench setup, connect rules, analog-digital co-simulation, RNM regression, and functional-coverage closure, ending in AMS sign-off. Invoke to verify a mixed-signal block across corners, or to re-validate after a fixrequest was serviced. Opens fixrequests routed to…
hdl-tools/analog-chip-design-agents
Skill Claude CodeCodex
Build mixed-signal testbenches, define connect rules, run analog-digital co-simulation and real-number-model regressions, and close functional coverage. Use when verifying an analog/mixed-signal block against its digital control across corners, or re-validating after a model/circuit fix. Opens fixrequests routed to…
hdl-tools/analog-chip-design-agents
Plugin Claude Code
Signal-chain budgeting, per-block spec allocation, and feasibility for analog/mixed-signal.
hdl-tools/analog-chip-design-agents
Agent
Orchestrates the Analog Architecture flow (speccapture → signalchainbudgeting → topologypartitioning → behavioralfeasibility → architecturesignoff). Invoke to budget an analog/mixed-signal signal chain from a system spec down to a feasible per-block specification contract that circuit-design consumes.
hdl-tools/analog-chip-design-agents
Skill Claude CodeCodex
Capture top-level analog/mixed-signal specs, budget noise/linearity/power across a signal chain, allocate per-block specifications, and assess feasibility before circuit design begins. Use when planning a receiver front-end, data-converter front-end, sensor AFE, PLL/clock, or PMIC from a system spec down to a…
hdl-tools/analog-chip-design-agents
Plugin Claude Code
Timing/power/noise characterization and Liberty (.lib) / behavioral model generation.
hdl-tools/analog-chip-design-agents
Agent
Orchestrates the characterization flow — timing, power, and noise across PVT corners — ending in a validated Liberty (.lib) + behavioral-model sign-off. Invoke to build the abstract views a chip-level / digital flow consumes from a signed-off, extracted analog macro, or to re-run after a setup fix. Loop-backs are…
hdl-tools/analog-chip-design-agents
Skill Claude CodeCodex
Characterize timing, power, and noise of a signed-off analog/mixed macro across PVT corners and generate validated Liberty (.lib) + behavioral models for downstream integration. Use when building the abstract views a chip-level / digital flow consumes, or re-running after a setup fix. Loop-backs are stage-local…
hdl-tools/analog-chip-design-agents
Plugin Claude Code
Topology selection, device sizing/biasing, schematic capture, pre-layout ERC and design review.
hdl-tools/analog-chip-design-agents
Agent
Orchestrates analog circuit (schematic) design — topology selection, gm/Id device sizing, biasing, schematic capture, pre-layout ERC, and design review. Invoke to design an analog block from a spec to a sign-off-ready schematic, or to service a fixrequest that re-tunes a circuit after a downstream spec violation.
hdl-tools/analog-chip-design-agents
Skill Claude CodeCodex
Analog circuit (schematic) design — topology selection, device sizing via gm/Id, biasing, schematic capture, pre-layout ERC, and design review. Use when designing an op-amp, comparator, bandgap, LDO, bias generator, or any analog block from a block specification through to a sign-off-ready schematic and netlist.
hdl-tools/analog-chip-design-agents
Plugin Claude Code
Electromagnetic solving for passives/antennas, S-parameter extraction and lumped-model fitting.
hdl-tools/analog-chip-design-agents
Agent
Orchestrates the EM-modeling flow (emsetup → geometrydefinition → meshing → emsolve → sparameterextraction → modelfitting → emsignoff), producing a converged, passive Touchstone S-parameter model + fitted lumped model for rf-design to consume. Invoke to solve an on-chip passive/antenna, or to service an rf-design…
hdl-tools/analog-chip-design-agents
Skill Claude CodeCodex
Solve the electromagnetics of an on-chip passive or antenna (inductor, transformer, transmission line, balun, antenna), extract a converged passive S-parameter model, and fit a lumped equivalent for circuit-level RF simulation. Use when building the passive model rf-design consumes, or to service an rf-design…
hdl-tools/analog-chip-design-agents
Plugin Claude Code
RC and coupling parasitic extraction and back-annotated post-layout netlist generation.
hdl-tools/analog-chip-design-agents
Agent
Orchestrates parasitic extraction — extraction setup, RC extraction, coupling extraction, netlist back-annotation, and PEX sign-off. Invoke to extract parasitics from a physically-clean layout and build the back-annotated post-layout netlist, gating on the pexsignoff checkpoint and flagging large degradation to…
hdl-tools/analog-chip-design-agents
Skill Claude CodeCodex
Run RC and coupling extraction on the verified layout and build a back-annotated post-layout netlist for sign-off simulation. Use when extracting parasitics from a physically-clean GDS, building the PEX netlist for post-layout sign-off, or flagging a layout for parasitic reduction.
hdl-tools/analog-chip-design-agents
Plugin Claude Code
Analog/RF tool detection, JSON output wrappers, MCP config, and memory distillation.