analog-design-modeling

A plugin for modeling analog and mixed-signal chip behavior with Verilog-A/AMS, VHDL-AMS, and SystemVerilog real-number models. It also includes OSDI compilation and connect modules.

In plain words
What is it for?
It is for behavioral modeling and related compilation or connection work in analog and mixed-signal chip design.
Why use it?
The provided description is limited to these supported analog-design modeling components.

Plugin for Claude Code

Install

Getting it into your agent

One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.

Claude Code
/plugin marketplace add hdl-tools/analog-chip-design-agents
agentmods
npx agentmods add plugins/hdl-tools/analog-chip-design-agents/modeling
Clone the repo
git clone --depth 1 https://github.com/hdl-tools/analog-chip-design-agents

Made for: Claude Code.

Per session not measured What this adds to a session before it is invoked.
When invoked not measured The manifest loads nothing itself; its 1 skill, 1 agent cost 157 tokens a session between them.
Security scan A 0 findings. Scan, not verified.
Origin 91% copy Near-identical to another mod in the catalogue.
Security

Grade A, and why

analog-design-modeling scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 3d ago.

A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.

Nothing flagged

None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.

Origin

This is a copy

91% identical to analog-design-ams-verification — 8 lines differ, which has more behind it and is treated as the original. This page carries a canonical link to it rather than competing with it.

plugins/modeling/.claude-plugin/plugin.json · 19 lines

What it actually says

{
  "name": "analog-design-modeling",
  "version": "0.1.0",
  "description": "Verilog-A/AMS, VHDL-AMS and SystemVerilog real-number modeling, OSDI compilation, connect modules",
  "author": {
    "name": "chuanseng-ng",
    "url": "https://github.com/chuanseng-ng"
  },
  "homepage": "https://github.com/chuanseng-ng/analog-chip-design-agents",
  "repository": "https://github.com/chuanseng-ng/analog-chip-design-agents",
  "license": "MIT",
  "skills": [
    "./skills/behavioral-modeling"
  ],
  "agents": [
    "./agents/behavioral-modeling-orchestrator.md"
  ]
}
Contents

What it installs

The manifest is a name and a version. 1 skill, 1 agent travel with it, and installing the plugin installs all of them — 157 tokens a session between them. Each is measured on its own page, and each can be installed alone.

Changes

What this file has done since we first saw it

Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.

  1. 3d ago First seen · 19 lines scan A 8cfb4dec3014

Subscribe to this mod's changes

analog-design-modeling is a plugin published in the GitHub repository hdl-tools/analog-chip-design-agents (22 stars, last pushed 2mo ago), licensed MIT. Its token cost is not measured: this kind of file is read by the harness, not the model. A static security scan graded it A with 0 findings. It is 91% identical to analog-design-ams-verification, differing in 8 lines, and is treated as a copy.

Related

Other plugins, from other repositories