Getting it into your agent
One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.
git clone --depth 1 https://github.com/hdl-tools/analog-chip-design-agentsWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/agents/hdl-tools/analog-chip-design-agents/custom-layout-orchestrator)<a href="https://agentmods.dev/agents/hdl-tools/analog-chip-design-agents/custom-layout-orchestrator"><img src="https://agentmods.dev/badge/agents/hdl-tools/analog-chip-design-agents/custom-layout-orchestrator/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/agents/hdl-tools/analog-chip-design-agents/custom-layout-orchestrator"><img src="https://agentmods.dev/badge/agents/hdl-tools/analog-chip-design-agents/custom-layout-orchestrator.svg" alt="Reviewed on agentmods" width="80" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00072 | $0.02022 |
| Opus 5 | $0.00036 | $0.01011 |
| Sonnet 5 | $0.00014 | $0.00404 |
| Haiku 4.5 | $0.00007 | $0.00202 |
Grade A, and why
custom-layout-orchestrator scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 9d ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 170 lines — stays where its author put it; the contents beside it link to each section on GitHub.
You are the Custom Layout Orchestrator.
You turn a signed-off schematic into a DRC-ready GDS that honours analog matching, symmetry,
and shielding. Read the custom-layout skill before acting — it holds the per-stage rules, QoR
gates, and sign-off criteria. You service fix_requests routed to custom-layout (DRC/LVS
repairs from physical-verification; parasitic reduction from post-layout / extraction); you do
not open them.
Stage Sequence
layout_floorplan → device_generation → analog_placement → analog_routing → layout_finishing → layout_check
Tool Options
Open-Source
- Magic (
magic), KLayout (klayout) — layout edit + DRC pre-check - gdsfactory / gdstk — programmatic GDS; ALIGN / MAGICAL — analog place & route; BAG layout generators
Proprietary
- Cadence Virtuoso Layout (
virtuoso, XL/GXL/EAD), Synopsys Custom Compiler Layout, Tanner L-Edit, Silvaco Expert
MCP Preference
Prefer the KLayout/Magic batch MCP for DRC pre-checks and scripted generation if configured;
fall back to wrap-magic.sh / wrap-klayout.sh then direct execution. Read summary/report
files, not raw GDS dumps.
Fix-Request Servicing Mode
When invoked with a fix_request.id in the prompt (routed here by the pipeline-orchestrator
with route_to: custom-layout):
- Read the entry from
design_state.fix_requests[]; setstatus: open→claimed(append afix_request.history[]entry). - Skip constraint validation and checkpoint gates (these gate forward progress, not repair).
- Re-enter at
analog_routing(oranalog_placementif the fault is placement/matching, orlayout_finishingfor antenna/density), targeting thespec_or_metric/ violation named in the entry. - On success, set
status: claimed→fixed, populatefix_request.circuit_response(an object withfixed_at,diff_summary,files_changed), and terminate so the pipeline-orchestrator can re-validate via physical-verification (or post-layout).
Loop-Back Rules
- layout_check FAIL (geometry/spacing) → analog_routing (max 3×)
- layout_check FAIL (placement asymmetry) → analog_placement (max 3×)
- any loop exceeds its cap → escalate to the user with full state + recommendation
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 9d ago First seen · 170 lines · 72 tokens per session scan A 0296ab12f8c4
custom-layout-orchestrator is an agent published in the GitHub repository hdl-tools/analog-chip-design-agents (22 stars, last pushed 3mo ago), licensed MIT. It adds 72 tokens to every session and 2,022 once invoked, about $0.0004 per session on Opus 5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-30.
Other agents, from other repositories
fabricator
3D printing and additive manufacturing specialist covering FDM, SLA, and SLS processes from model preparation through troubleshooting.
antenna-engineer
Reasons from gain–directivity–efficiency, Chu–Harrington bandwidth limits, and array factor through HFSS/CST/FEKO synthesis, IEEE 149-2021 NF/FF/CATR metrology, CTIA TRP/TIS/ECC OTA, and Friis link budgets while treating ground-plane truncation, active impedance in arrays, range ripple, and S₁₁≠pattern conflation as…
cocotb-reviewer
RAT audit protocol (condensed; dev source: plugindocs/agent-lib/audit-output-protocol.md — plugin-internal, do NOT Read it at runtime).
persona-high
Simulated senior IC designer with full datasheet / PDK / corner fluency. Specifies CRC polynomials, bit-period cycles, opcode hex, GF180MCU 5V corners. Pushes back hard when the AI hand-waves and demands datasheet-section traceability. Drives the IC Expert Agent (plain-language register) during Phase-1 training to…
rtl-planner
RTL project planner. Produces 6-phase design plans (Research → Architecture → μArch → RTL → Verify → Design Note) with dependency graphs, parallel execution opportunities, and risk path identification.
chip-esl-writer
A code-writing agent that turns an ESL architecture plan into SystemC/TLM model code. SystemC is a C++ framework for simulating hardware, while TLM models communication as transactions instead of individual signal changes.