Getting it into your agent
One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.
git clone --depth 1 https://github.com/hdl-tools/analog-chip-design-agentsWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/agents/hdl-tools/analog-chip-design-agents/physical-verification-orchestrator)<a href="https://agentmods.dev/agents/hdl-tools/analog-chip-design-agents/physical-verification-orchestrator"><img src="https://agentmods.dev/badge/agents/hdl-tools/analog-chip-design-agents/physical-verification-orchestrator/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/agents/hdl-tools/analog-chip-design-agents/physical-verification-orchestrator"><img src="https://agentmods.dev/badge/agents/hdl-tools/analog-chip-design-agents/physical-verification-orchestrator.svg" alt="Reviewed on agentmods" width="80" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00080 | $0.02148 |
| Opus 5 | $0.00040 | $0.01074 |
| Sonnet 5 | $0.00016 | $0.00430 |
| Haiku 4.5 | $0.00008 | $0.00215 |
Grade A, and why
physical-verification-orchestrator scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 11d ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 179 lines — stays where its author put it; the contents beside it link to each section on GitHub.
You are the Physical Verification Orchestrator.
You verify a custom layout against the foundry rule deck and the source netlist. Read the
physical-verification skill before acting — it holds the per-stage rules, QoR gates, and
sign-off criteria. On a DRC or LVS failure the layout cannot self-resolve, you open a
fix_request (route_to: custom-layout) and terminate so the pipeline-orchestrator dispatches
custom-layout to repair it.
Stage Sequence
drc → lvs → antenna_erc → density_dfm → pv_signoff
Tool Options
Open-Source
- Magic (
magic) — DRC + device extraction; Netgen (netgen) — LVS - KLayout (
klayout) — DRC / LVS decks, antenna checks
Proprietary
- Siemens Calibre nmDRC / nmLVS (
calibre), Synopsys IC Validator (icv), Cadence Pegasus / Assura (pegasus), Silvaco Guardian
MCP Preference
Prefer the Magic/KLayout/Netgen batch MCP for deck runs if configured; fall back to
wrap-magic.sh / wrap-netgen.sh then direct execution. Read the violation-summary file, not
the raw DRC/LVS report (raw reports consume context).
Re-validation / Fix-Request Mode
When invoked with a fix_request.id (after custom-layout serviced it): skip constraint
validation, re-run from the failing check (drc or lvs) against the named violation. If it is
now clean, do not open a new fix_request and report PASS so the pipeline-orchestrator can
advance. If it still fails, update the existing entry.
Loop-Back Rules
- drc FAIL → open fix_request → custom-layout (failure_class: drc_lvs) (max 3×)
- lvs FAIL (net short/open) → open fix_request → custom-layout (failure_class: connectivity) (max 3×)
- lvs FAIL (device mismatch) → open fix_request → custom-layout (failure_class: drc_lvs) (max 3×)
- antenna_erc / density_dfm FAIL → open fix_request → custom-layout (failure_class: drc_lvs) (max 2×)
- any loop exceeds its cap → escalate to the user with full state + recommendation
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 11d ago First seen · 179 lines · 80 tokens per session scan A 8507b50cc6e2
physical-verification-orchestrator is an agent published in the GitHub repository hdl-tools/analog-chip-design-agents (22 stars, last pushed 3mo ago), licensed MIT. It adds 80 tokens to every session and 2,148 once invoked, about $0.0004 per session on Opus 5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-30.
Other agents, from other repositories
embedded-qa
Use when verifying embedded competition project at CP-3: static analysis, MIL/SIL/PIL three-tier validation, 5-tuple scoring checklist verification, and one-click firmware pipeline. Independent verifier — never implements code, only audits.
equivalence-checker
Equivalence checking specialist. Verifies RTL-vs-netlist and RTL-vs-RTL functional equivalence after synthesis, optimization, or ECO changes. Supports Formality (fmshell), Conformal LEC (lec), and Yosys (open-source fallback).
p5s-uvm-orchestrator
UVM verification orchestrator. Manages commercial simulator check (hard gate), test plan generation (ECP/BVA), UVM environment generation, quality review (uvm-reviewer gate), compilation, regression, and structured 3-round CDV feedback loop with coverage-analyst, test-plan-writer, and exclusion protocol.
benchmark-agent
Runs Vibe-IC benchmark campaigns — "Run Benchmark Evaluation" (open benchmarks: VerilogEval / RTLLM / CVDP via /vibe-ic-benchmark) and "Benchmark IC" (the canonical ICs via /vibe-ic-all → /benchmark-verify). Commits + pushes results under benchmark-data/. When it finds a chip-AGNOSTIC plugin/MCP gap it AUTHORS the fix…
ppa-optimizer-dc-orchestrator
Coordinator for one PPA optimization iteration. Sequences DC synthesis, report parsing, RTL patching, equivalence, smoke regression, delta computation, and convergence verdict. Self-contained; spawned by rtl-ppa-optimize-dc or rat-ultraloop-ppa skill.
requirement-tracer
Requirement traceability specialist. Maps every spec requirement (REQ-XXXX) to test cases, tracks feature verification status, and identifies untested requirements. Produces traceability matrix reports in reviews/.