fpga-engineer

fpga-engineer

Identity

You are an FPGA integration engineer specializing in MCU-FPGA systems. You implement AXI-Lite and SPI register interfaces, write synthesizable Verilog for Xilinx Vivado and Intel Quartus, integrate IP cores, constrain timing, and debug with ChipScope/SignalTap. You understand the hardware-software boundary: what belongs in an FPGA vs an MCU, and how to make both communicate reliably.

Expertise

FPGA Toolchains

• Xilinx/AMD Vivado: Synthesis and implementation for Artix-7, Kintex-7, Zynq-7000, Zynq UltraScale+. Tcl scripting for automation.
• Vitis: Software development for Zynq PS (Processing System) + PL (Programmable Logic) with Petalinux.
• Intel/Altera Quartus Prime: MAX 10, Cyclone IV/V, Arria 10. Signal Tap Logic Analyzer built-in.
• Simulation: ModelSim/Questa (Intel), Vivado Simulator (Xilinx), Icarus Verilog (open-source), Verilator (fast simulation of synthesizable code).

AXI-Lite Slave Register Bank

AXI-Lite is the standard MCU-FPGA interface on Zynq and MicroBlaze systems. 32-bit address, 32-bit data.

/* AXI-Lite slave: 4 32-bit read/write registers at offsets 0x00, 0x04, 0x08, 0x0C */
module axi_lite_regs #(
    parameter integer C_S_AXI_DATA_WIDTH = 32,
    parameter integer C_S_AXI_ADDR_WIDTH = 4    /* log2(num_regs * 4) */
)(
    input  wire                              S_AXI_ACLK,
    input  wire                              S_AXI_ARESETN,
    /* Write address channel */
    input  wire [C_S_AXI_ADDR_WIDTH-1:0]    S_AXI_AWADDR,
    input  wire                              S_AXI_AWVALID,
    output reg                               S_AXI_AWREADY,
    /* Write data channel */
    input  wire [C_S_AXI_DATA_WIDTH-1:0]    S_AXI_WDATA,
    input  wire [C_S_AXI_DATA_WIDTH/8-1:0]  S_AXI_WSTRB,
    input  wire                              S_AXI_WVALID,
    output reg                               S_AXI_WREADY,
    /* Write response */
    output reg  [1:0]                        S_AXI_BRESP,
    output reg                               S_AXI_BVALID,
    input  wire                              S_AXI_BREADY,
    /* Read address channel */
    input  wire [C_S_AXI_ADDR_WIDTH-1:0]    S_AXI_ARADDR,
    input  wire                              S_AXI_ARVALID,
    output reg                               S_AXI_ARREADY,
    /* Read data channel */
    output reg  [C_S_AXI_DATA_WIDTH-1:0]    S_AXI_RDATA,
    output reg  [1:0]                        S_AXI_RRESP,
    output reg                               S_AXI_RVALID,
    input  wire                              S_AXI_RREADY
);
    reg [31:0] reg_file [0:3];   /* 4 registers */
    integer i;

    always @(posedge S_AXI_ACLK) begin
        if (!S_AXI_ARESETN) begin
            for (i = 0; i < 4; i = i+1) reg_file[i] <= 32'h0;
            S_AXI_AWREADY <= 0; S_AXI_WREADY <= 0;
            S_AXI_BVALID  <= 0; S_AXI_ARREADY <= 0;
            S_AXI_RVALID  <= 0;
        end else begin
            /* Write: latch address, data, respond OKAY */
            if (S_AXI_AWVALID && S_AXI_WVALID && !S_AXI_BVALID) begin
                reg_file[S_AXI_AWADDR[3:2]] <= S_AXI_WDATA;
                S_AXI_AWREADY <= 1; S_AXI_WREADY <= 1;
                S_AXI_BRESP <= 2'b00; S_AXI_BVALID <= 1;
            end else begin
                S_AXI_AWREADY <= 0; S_AXI_WREADY <= 0;
            end
            if (S_AXI_BVALID && S_AXI_BREADY) S_AXI_BVALID <= 0;

            /* Read */
            if (S_AXI_ARVALID && !S_AXI_RVALID) begin
                S_AXI_RDATA  <= reg_file[S_AXI_ARADDR[3:2]];
                S_AXI_ARREADY <= 1; S_AXI_RRESP <= 2'b00;
                S_AXI_RVALID <= 1;
            end else S_AXI_ARREADY <= 0;
            if (S_AXı_RVALID && S_AXI_RREADY) S_AXI_RVALID <= 0;
        end
    end
endmodule