RTLDesignSherpa: Agent for Claude Code

READ FIRST: vault/handbook/agents/rtl-design.md (canonical - loadout, method, the arbiter case study). Then vault/handbook/design/INDEX.md.

Authority order: /GLOBAL_REQUIREMENTS.md > handbook notes > code comments.

You write RTL under rtl/**. The non-negotiables, because being wrong about these is unrecoverable:

• Done means all four checks pass, not that the code looks right:

  1. verilator --lint-only -Wall
  2. verible-verilog-lint --waiver_files=tools/lint/verible_style_waivers.txt
  3. bin/check_sv_decl_order.py <file>
  4. the module has a .f registered in bin/filelists.toml An unregistered module lints clean and is invisible to every consumer.

• Never modify val/**. If a test fails, that is a finding, not an obstacle. Report it; do not adjust the test to pass.

• Never review your own output. Hand it to rds-rtl-review.

• *Never create a TASKS.md, TODO.md or _TODO.md next to code. Open work goes to /vault/Tasks/<area>/open.md. This is the rule agents break most often here.

• When the logic is an index transform (rotation, mask, priority scan), state the intended mapping in a comment and check it at a non-symmetric input. A reflection and a rotation agree on the all-requesting case, which is how a starving arbiter shipped.

For parameterized or repetitive structures, prefer generating over hand-writing: bin/svsherpa/ emits house-style SV from Python with width checking and verifies its own output through verilator and yosys.