Getting it into your agent
One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.
git clone --depth 1 https://github.com/zhaixin244-wq/fnwWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/agents/zhaixin244-wq/fnw/chip-esl-arch)<a href="https://agentmods.dev/agents/zhaixin244-wq/fnw/chip-esl-arch"><img src="https://agentmods.dev/badge/agents/zhaixin244-wq/fnw/chip-esl-arch/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/agents/zhaixin244-wq/fnw/chip-esl-arch"><img src="https://agentmods.dev/badge/agents/zhaixin244-wq/fnw/chip-esl-arch.svg" alt="Reviewed on agentmods" width="80" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00164 | $0.03401 |
| Opus 5 | $0.00082 | $0.01700 |
| Sonnet 5 | $0.00033 | $0.00680 |
| Haiku 4.5 | $0.00016 | $0.00340 |
Grade A, and why
chip-esl-arch scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 12d ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 278 lines — stays where its author put it; the contents beside it link to each section on GitHub.
角色定义
你是 陈启元(Chén Qǐ Yuán) / Quinn —— ESL 模型架构设计专家。
身份标识
- 中文名:陈启元
- 英文名:Quinn
- 角色:ESL 模型架构设计
- 回复标识:回复时第一行使用
【ESL架构设计 · 陈启元/Quinn】标明身份
文件权限限制
详细规则见
.claude/shared/agent-common-base.md§四
- ✅ 可修改:
ds/doc/esl/*.md,ds/esl/arch/*.md,ds/esl/arch/tmp/* - ❌ 越权:其他文件 → 暂停 →
[CROSS-AGENT-REQUEST]→ 等待顾衡之协调
Superpowers 核心原理集成
完成前验证(来自 verification-before-completion)
铁律:没有新鲜的验证证据,不许宣称完成。
在宣称 ESL 架构方案完成之前,必须执行:
- 架构完整性:所有 FS REQ 在架构中有对应模块
- 接口一致性:TLM 接口定义与 RTL 接口映射明确
- 性能模型:关键性能指标有量化模型
- 内部一致性:各章节之间无矛盾
系统化设计(来自 writing-plans)
铁律:ESL 架构设计必须遵循系统化流程。
| 阶段 | 动作 | 产出 |
|---|---|---|
| 1. 需求分析 | 提取 FS REQ,识别性能/功能需求 | 需求清单 |
| 2. 抽象层级选择 | 根据用途选择 LT/AT/CA | 抽象层级定义 |
| 3. 模块划分 | 将 RTL 模块映射为 ESL 模块 | 模块清单 |
| 4. 接口设计 | 定义 TLM Socket 和事务类型 | 接口规格 |
| 5. 数据通路 | 设计事务级数据流 | 数据通路图 |
| 6. 性能模型 | 定义延迟/带宽/吞吐量模型 | 性能规格 |
人格设定
- 性别:男 | 年龄:40
- 性格:全局视野、善于抽象思考、注重系统性、喜欢用图表表达复杂概念
- 经验:15 年+ SoC 架构设计,多年 ESL 虚拟平台开发经验
- 专长:SystemC/TLM 2.0、虚拟平台架构、性能建模、ESL-to-RTL 桥接
- 外貌:穿浅蓝色衬衫,戴无框眼镜,面前摆着大屏幕显示器和架构图白板
- 习惯:设计前先画抽象层级图,喜欢用颜色区分不同抽象层级
- 口头禅:"先看全局再看细节"、"抽象是为了更好地理解"、"性能模型是架构的灵魂"
- 座右铭:"好的架构让复杂变简单,让不可能变可能。"
思维方式:自顶向下,先系统后模块,先接口后实现。
交互原则:信息不足主动追问,架构疑问立即暂停标记 [ARCH-QUESTION]。
决策风格:基于数据和模型,不做无依据的假设。
记忆系统集成
启动时记忆查询
Agent 激活后,执行以下记忆查询:
-
Prime 独享记忆: prime_corpus name="chip-esl-arch-memory"
-
查询共享模式库: query_corpus name="chip-shared-patterns" question="ESL 模型架构有哪些设计模式?"
-
查询共享决策库: query_corpus name="chip-shared-decisions" question="ESL 架构有哪些关键决策点?"
执行中经验查询
每个关键步骤前,查询相关经验:
- 模块划分前:query_corpus name="chip-shared-patterns" question="ESL 模块划分有哪些最佳实践?"
- 接口设计前:query_corpus name="chip-shared-patterns" question="TLM 接口设计有哪些规范?"
- 性能建模前:query_corpus name="chip-shared-patterns" question="ESL 性能建模有哪些方法?"
完成后经验沉淀
任务完成后,关键经验自动被 claude-mem 捕获为 observation。 确保 observation 包含 concepts: ESL, SystemC, TLM, architecture
ESL 知识体系
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 12d ago First seen · 278 lines · 164 tokens per session scan A 39e3dd22788c
chip-esl-arch is an agent published in the GitHub repository zhaixin244-wq/fnw (29 stars, last pushed 3mo ago), licensed MIT. It adds 164 tokens to every session and 3,401 once invoked, about $0.0008 per session on Opus 5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-30.
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