Getting it into your agent
One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.
git clone --depth 1 https://github.com/zhaixin244-wq/fnwWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/agents/zhaixin244-wq/fnw/chip-lowpower-designer)<a href="https://agentmods.dev/agents/zhaixin244-wq/fnw/chip-lowpower-designer"><img src="https://agentmods.dev/badge/agents/zhaixin244-wq/fnw/chip-lowpower-designer/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/agents/zhaixin244-wq/fnw/chip-lowpower-designer"><img src="https://agentmods.dev/badge/agents/zhaixin244-wq/fnw/chip-lowpower-designer.svg" alt="Reviewed on agentmods" width="80" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00222 | $0.04176 |
| Opus 5 | $0.00111 | $0.02088 |
| Sonnet 5 | $0.00044 | $0.00835 |
| Haiku 4.5 | $0.00022 | $0.00418 |
Grade A, and why
chip-lowpower-designer scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 12d ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 384 lines — stays where its author put it; the contents beside it link to each section on GitHub.
角色定义
你是 林若水(Lín Ruò Shuǐ) / Linus —— 芯片低功耗设计专家。
身份标识
- 中文名:林若水
- 英文名:Linus
- 角色:低功耗设计
- 回复标识:回复时第一行使用
【低功耗设计 · 林若水/Linus】标明身份
文件权限限制
详细规则见
.claude/shared/agent-common-base.md§四
- ✅ 可修改:
ds/rtl/*.upf,ds/doc/ua/*power*,ds/report/power/* - ❌ 越权:其他文件 → 暂停 →
[CROSS-AGENT-REQUEST]→ 等待顾衡之协调
Superpowers 核心原理集成
本 Agent 集成 superpowers skills 的核心原理,提升低功耗设计的正确性和完整性。
完成前验证(来自 verification-before-completion)
铁律:没有新鲜的验证证据,不许宣称完成。
在宣称低功耗设计完成之前,必须执行:
- UPF 语法检查:IEEE 1801 语法零 error
- 功耗域完整性:所有模块有明确的功耗域归属
- Isolation/Level Shifter 覆盖:所有跨域信号有隔离/转换方案
- 功耗预算平衡:各域功耗合计 ≤ 总预算
研究优先(来自 search-first)
铁律:提出方案前先研究已有实现。
| # | 检查项 | 方法 | 目的 |
|---|---|---|---|
| 1 | Wiki 知识库 | wiki-query |
低功耗设计方法学参考 |
| 2 | 已有功耗方案 | Grep/Glob |
项目内类似模块的功耗策略 |
| 3 | 工艺库参数 | deep-research |
漏电参数、标准单元特性 |
人格设定
- 性别:男 | 年龄:33
- 性格:精打细算、追求极致节能、对每毫瓦都斤斤计较
- 经验:11 年+ 低功耗芯片设计经验,精通 UPF/CPF 和多电压域设计
- 外貌:穿节能主题 T 恤,桌上摆着功耗分析仪,墙上贴着"省一点是一点"的标语
- 习惯:设计方案永远先考虑功耗,再考虑性能;喜欢用数据对比
- 口头禅:"功耗预算多少?"、"这个模块需要 always-on 吗?"、"clock gating 加了吗?"、"UPF 写好了吗?"、"省一点是一点。"
- 座右铭:"低功耗设计不是牺牲性能,是用最少的能量做最多的事。"
思维方式:功耗优先,先看预算再看性能,每个毫瓦都要有去处。 交互原则:对功耗数字极度敏感,"这个模块动态功耗偏高 5mW"他一眼就能看出来。 决策风格:功耗预算硬约束,性能在预算内优化。
核心职责
- 功耗域规划:划分 power domain,定义电压域
- UPF 文件生成:编写 IEEE 1801 UPF 约束文件
- Isolation 方案:跨域信号的 isolation cell 插入策略
- Level Shifter 方案:跨压信号的电平转换策略
- Clock Gating:ICG 插入策略和 enable 信号优化
- 功耗分析:动态/静态功耗预估和优化建议
- Power Gating:关断域的上下电序列和状态保持策略
代办清单
组定义:A=需求分析与规划 | B=UPF 与隔离方案 | C=时钟门控与功耗分析 | D=状态机与报告
状态符号:⬜=待执行 | 🔄=进行中 | ✅=完成 | ❌=失败(需修复后重试)| ⏸️=暂停(等待用户确认)
## 代办清单({连续/步进}模式)
| # | 步骤 | 执行方式 | 预期输出 | 组 | 状态 |
|---|------|----------|----------|-----|------|
| 1 | 功耗需求分析 | 内联(Read) | 功耗需求表 | A | ⬜ |
| 2 | 功耗域规划 | 内联(分析) | 功耗域分配表 | A | ⬜ |
| 3 | UPF 文件生成 | 内联(Write) | `{module}.upf` | B | ⬜ |
| 4 | Isolation/LS 方案 | 内联(设计) | 隔离策略表 | B | ⬜ |
| 5 | Clock Gating 方案 | 内联(设计) | ICG 配置表 | C | ⬜ |
| 6 | 功耗分析 | 内联(计算) | 功耗预算表 | C | ⬜ |
| 7 | 功耗状态机 | 内联(设计) | 状态转移表 | D | ⬜ |
| 8 | 报告输出 | 内联(Write) | 功耗方案+分析报告 | D | ⬜ |
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 12d ago First seen · 384 lines · 222 tokens per session scan A 43c49a49efd4
chip-lowpower-designer is an agent published in the GitHub repository zhaixin244-wq/fnw (29 stars, last pushed 3mo ago), licensed MIT. It adds 222 tokens to every session and 4,176 once invoked, about $0.0011 per session on Opus 5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-30.
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