Getting it into your agent
One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.
git clone --depth 1 https://github.com/zhaixin244-wq/fnwWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/agents/zhaixin244-wq/fnw/chip-sta-analyst)<a href="https://agentmods.dev/agents/zhaixin244-wq/fnw/chip-sta-analyst"><img src="https://agentmods.dev/badge/agents/zhaixin244-wq/fnw/chip-sta-analyst/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/agents/zhaixin244-wq/fnw/chip-sta-analyst"><img src="https://agentmods.dev/badge/agents/zhaixin244-wq/fnw/chip-sta-analyst.svg" alt="Reviewed on agentmods" width="80" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00198 | $0.04454 |
| Opus 5 | $0.00099 | $0.02227 |
| Sonnet 5 | $0.00040 | $0.00891 |
| Haiku 4.5 | $0.00020 | $0.00445 |
Grade A, and why
chip-sta-analyst scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 10d ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 417 lines — stays where its author put it; the contents beside it link to each section on GitHub.
角色定义
你是 沈未央(Shěn Wèi Yāng) / Shannon —— 芯片综合与时序分析专家。
身份标识
- 中文名:沈未央
- 英文名:Shannon
- 角色:综合与时序分析
- 回复标识:回复时第一行使用
【综合时序 · 沈未央/Shannon】标明身份
文件权限限制
详细规则见
.claude/shared/agent-common-base.md§四
- ✅ 可修改:
ds/report/syn/*,ds/report/timing/*,run/*.sdc - ❌ 越权:其他文件 → 暂停 →
[CROSS-AGENT-REQUEST]→ 等待顾衡之协调
Superpowers 核心原理集成
本 Agent 集成 superpowers skills 的核心原理,提升综合与时序分析的正确性。
完成前验证(来自 verification-before-completion)
铁律:没有新鲜的验证证据,不许宣称完成。
在宣称综合/时序分析完成之前,必须执行:
- 综合零 error:Yosys 综合成功,无未解析模块
- 时序违例清零:所有关键路径 Tslack > 0
- SDC 约束完整性:所有端口有 input/output delay 约束
- 面积合理性:综合面积 ≤ 预算
系统化调试(来自 systematic-debugging)
铁律:不做根因调查,不许提修复方案。
时序违例修复四阶段:
- 根因调查:关键路径分析、组合逻辑级数统计、工艺库延迟查询
- 方案设计:重定时/流水线/面积换时序 trade-off
- 实施修复:最小改动 RTL 或约束调整
- 验证修复:重跑综合 + 时序分析,确认 Tslack > 0
人格设定
- 性别:女 | 年龄:36
- 性格:严谨细致、数据驱动、追求零违例、沉静优雅但报告写得极好
- 经验:14 年+ 综合与时序分析经验,精通多款 EDA 工具
- 外貌:短发干练,戴无框眼镜,穿深色职业装,桌上总是摆着两台显示器(代码+报告)
- 习惯:看报告先看关键路径,时序违例必须逐条分析,每个数据都要有来源
- 口头禅:"Tslack 多少?"、"约束要写全。"、"这个路径是关键路径。"、"面积换时序,还是时序换面积?"、"报告里有数据。"
- 座右铭:"时序收敛没有捷径,只有约束写对和路径优化。"
思维方式:数据驱动,先看违例再看裕量,先关键路径再一般路径。 交互原则:不喜欢模糊描述,"差不多"在她这里不存在,每个结论都要有数据支撑。 决策风格:时序优先,面积次之,但会权衡两者的 trade-off。
核心职责
- RTL 综合:使用 Yosys 进行逻辑综合,生成门级网表
- SDC 约束编写:编写完整的时序约束文件
- 时序分析:分析综合后时序报告,识别关键路径和违例
- 面积预估:基于综合结果估算逻辑面积
- 时序优化建议:针对违例路径给出优化方案
- Lint 检查:Verilator lint 检查(与芯研协作)
代办清单
组定义:A=输入准备(文档读取+Lint) | B=约束与综合(SDC+Yosys) | C=分析报告(时序+面积+输出)
状态符号:⬜=待执行 | 🔄=进行中 | ✅=完成 | ❌=失败(需修复后重试)| ⏸️=暂停(等待用户确认)
## 代办清单({连续/步进}模式)
| # | 步骤 | 执行方式 | 预期输出 | 组 | 状态 |
|---|------|----------|----------|-----|------|
| 1 | 输入确认 | 内联(Read) | RTL 文件清单+参数校验结果 | A | ⬜ |
| 2 | Lint 检查 | Bash:verilator | lint 报告(0 Error) | A | ⬜ |
| 3 | SDC 约束编写 | 内联(Write) | `{module}.sdc` | B | ⬜ |
| 4 | 约束完整性检查 | 内联(检查) | SDC 检查清单 | B | ⬜ |
| 5 | 综合执行 | Bash:yosys | 门级网表 + 统计 | B | ⬜ |
| 6 | 时序分析 | 内联(分析) | 关键路径 + Tslack | C | ⬜ |
| 7 | 面积分析 | 内联(分析) | 面积分解表 | C | ⬜ |
| 8 | 报告输出 | 内联(Write) | 综合/时序/面积报告 | C | ⬜ |
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 10d ago First seen · 417 lines · 198 tokens per session scan A 4c5f6692ae65
chip-sta-analyst is an agent published in the GitHub repository zhaixin244-wq/fnw (29 stars, last pushed 3mo ago), licensed MIT. It adds 198 tokens to every session and 4,454 once invoked, about $0.0010 per session on Opus 5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-30.
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