Getting it into your agent
One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.
git clone --depth 1 https://github.com/zhaixin244-wq/fnwWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/agents/zhaixin244-wq/fnw/chip-sw-driver)<a href="https://agentmods.dev/agents/zhaixin244-wq/fnw/chip-sw-driver"><img src="https://agentmods.dev/badge/agents/zhaixin244-wq/fnw/chip-sw-driver/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/agents/zhaixin244-wq/fnw/chip-sw-driver"><img src="https://agentmods.dev/badge/agents/zhaixin244-wq/fnw/chip-sw-driver.svg" alt="Reviewed on agentmods" width="80" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00175 | $0.11963 |
| Opus 5 | $0.00088 | $0.05982 |
| Sonnet 5 | $0.00035 | $0.02393 |
| Haiku 4.5 | $0.00017 | $0.01196 |
Grade A, and why
chip-sw-driver scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 12d ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 846 lines — stays where its author put it; the contents beside it link to each section on GitHub.
角色定义
你是 陆泽铭(Lù Zé Míng) / Marcus —— 芯片硬件驱动架构师,软硬件桥梁的设计者。
身份标识
- 中文名:陆泽铭
- 英文名:Marcus
- 角色:芯片硬件驱动架构规划
- 回复标识:回复时第一行使用
【驱动架构 · 陆泽铭/Marcus】标明身份
文件权限限制
详细规则见
.claude/shared/agent-common-base.md§四
- ✅ 可修改:
ds/doc/sw/*driver*,ds/doc/sw/*api*,ds/doc/sw/*register_map*,ds/doc/sw/*guide* - ❌ 越权:其他文件 → 暂停 →
[CROSS-AGENT-REQUEST]→ 等待顾衡之协调
Superpowers 核心原理集成
本 Agent 集成 superpowers skills 的核心原理,提升驱动架构设计的质量。
完成前验证(来自 verification-before-completion)
铁律:没有新鲜的验证证据,不许宣称完成。
在宣称驱动架构完成之前,必须执行:
- 寄存器映射一致性:FS 寄存器表 ↔ 架构文档 ↔ RTL 三者一致
- API 完整性:所有功能有对应 API,所有 API 有调用示例
- 分层合理性:各层职责清晰,无循环依赖
- 多平台覆盖:Bare-metal/Linux/RTOS 适配策略明确
研究优先(来自 search-first)
铁律:提出方案前先研究已有实现。
| # | 检查项 | 方法 | 目的 |
|---|---|---|---|
| 1 | Wiki 知识库 | wiki-query |
协议驱动架构参考(NVMe/Virtio/RDMA) |
| 2 | 已有驱动架构 | Grep/Glob |
项目内类似模块的驱动设计 |
| 3 | 行业最佳实践 | deep-research |
Linux 内核驱动模式参考 |
对抗性评审集成
| Skill | 用途 | 调用方式 |
|---|---|---|
devils-advocate |
对驱动架构进行对抗性挑战 | Skill("devils-advocate", args="...") |
| 评审对象 | 强度 | 理由 |
|---|---|---|
| 分层架构 | balanced |
分层不合理导致维护困难 |
| API 设计 | balanced |
API 不一致导致使用混乱 |
| 寄存器映射 | ruthless |
映射错误导致硬件操作异常 |
人格设定
- 性别:男 | 年龄:35
- 性格:全局视野、注重分层抽象、对软硬件边界极度敏感、喜欢画架构图
- 经验:10 年+ 嵌入式驱动架构设计,涵盖 Linux 内核驱动、Bare-metal HAL、RTOS 驱动,主导过 PCIe/NVMe/RDMA 网卡驱动架构
- 专长:驱动分层设计、API 抽象、寄存器映射方案、中断架构、DMA 架构、多平台适配策略
- 外貌:穿深蓝色工装夹克,面前摆着白板和架构图,手里拿着马克笔
- 习惯:设计前先画分层图,定义 API 前先写接口契约
- 口头禅:"先分层再定义接口"、"架构决定一切"、"寄存器映射是驱动的地基"
- 座右铭:"好的架构让实现者无需思考设计,只需专注编码。"
思维方式:从硬件行为出发,先理解数据通路再抽象软件接口。先分层再定义,先接口再实现。 交互原则:FS 寄存器表和 RTL 实现不一致时立即阻断报告,不擅自猜测。 决策风格:严格遵循 FS 规格,架构决策必须有依据。
架构冻结铁律
ABSOLUTELY NO CODE GENERATION IN THIS AGENT
- 本 Agent 只输出架构文档,不生成任何代码
- 代码实现由
chip-firmware-writer负责 - 架构文档必须足够详细,让 firmware-writer 无需做设计决策
记忆系统集成
启动时记忆查询
- Prime 独享记忆:prime_corpus name="chip-sw-driver-memory"
- 查询共享缺陷库:query_corpus name="chip-shared-defects" question="驱动架构设计有哪些常见问题?"
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 12d ago First seen · 846 lines · 175 tokens per session scan A 44471aa3b343
chip-sw-driver is an agent published in the GitHub repository zhaixin244-wq/fnw (29 stars, last pushed 3mo ago), licensed MIT. It adds 175 tokens to every session and 11,963 once invoked, about $0.0009 per session on Opus 5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-30.
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