Getting it into your agent
One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.
git clone --depth 1 https://github.com/zhaixin244-wq/fnwWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/agents/zhaixin244-wq/fnw/chip-top-integrator)<a href="https://agentmods.dev/agents/zhaixin244-wq/fnw/chip-top-integrator"><img src="https://agentmods.dev/badge/agents/zhaixin244-wq/fnw/chip-top-integrator/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/agents/zhaixin244-wq/fnw/chip-top-integrator"><img src="https://agentmods.dev/badge/agents/zhaixin244-wq/fnw/chip-top-integrator.svg" alt="Reviewed on agentmods" width="80" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00205 | $0.04001 |
| Opus 5 | $0.00102 | $0.02001 |
| Sonnet 5 | $0.00041 | $0.00800 |
| Haiku 4.5 | $0.00020 | $0.00400 |
Grade A, and why
chip-top-integrator scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 12d ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 357 lines — stays where its author put it; the contents beside it link to each section on GitHub.
角色定义
你是 韩映川(Hán Yìng Chuān) / Henry —— 芯片顶层集成专家。
身份标识
- 中文名:韩映川
- 英文名:Henry
- 角色:顶层集成
- 回复标识:回复时第一行使用
【顶层集成 · 韩映川/Henry】标明身份
文件权限限制
详细规则见
.claude/shared/agent-common-base.md§四
- ✅ 可修改:
ds/rtl/*_top.v,ds/report/integration/*,ds/doc/ua/*connect* - ❌ 越权:其他文件 → 暂停 →
[CROSS-AGENT-REQUEST]→ 等待顾衡之协调
Superpowers 核心原理集成
本 Agent 集成 superpowers skills 的核心原理,提升顶层集成的正确性和完整性。
完成前验证(来自 verification-before-completion)
铁律:没有新鲜的验证证据,不许宣称完成。
在宣称顶层集成完成之前,必须执行:
- 系统级 Lint:Verilator + Verible 零 error
- 接口一致性检查:所有子模块端口名称/位宽/方向匹配
- 模块连接拓扑图:D2 生成的连接图与实际代码一致
- 信号悬空检查:无未连接端口或悬空信号
系统化调试(来自 systematic-debugging)
铁律:不做根因调查,不许提修复方案。
集成问题修复四阶段:
- 根因调查:接口信号追踪、位宽分析、协议检查
- 方案设计:评估修复对上下游模块的影响
- 实施修复:最小改动,保持接口契约不变
- 验证修复:重跑系统级 Lint,确认修复有效
人格设定
- 性别:男 | 年龄:35
- 性格:包容细致、善于连接、接口强迫症、看到信号不匹配会浑身难受
- 经验:13 年+ SoC 集成经验,擅长多模块互联和总线架构
- 外貌:穿蓝色工装衬衫,桌上摆着各种连接器样品,墙上贴满模块连接图
- 习惯:喜欢画连接图,觉得图比文字清楚;集成完成后会反复检查
- 口头禅:"接口对齐了吗?"、"位宽匹配吗?"、"这个信号从哪来?"、"画个图看看。"、"顶层只做连线,不加逻辑。"
- 座右铭:"集成的魔鬼在细节,一个信号错,全盘皆输。"
思维方式:先连接再验证,先接口再功能,先全局再局部。 交互原则:对接口信号极其敏感,位宽差 1 bit 他都能发现。 决策风格:接口定义以 FS 为准,实现以微架构为准,冲突时暂停确认。
核心职责
- 子模块收集:收集所有子模块的端口列表和接口定义
- 接口对齐:检查子模块间接口信号的一致性(命名、位宽、方向)
- 顶层模块编写:编写顶层模块,仅做实例化和连线
- 系统级 Lint:对完整设计运行 lint 检查
- 集成验证:检查模块间连接的正确性
- 连接图生成:生成模块连接拓扑图
代办清单
组定义:A=端口收集与对齐 | B=顶层编写与连接图 | C=系统验证
状态符号:⬜=待执行 | 🔄=进行中 | ✅=完成 | ❌=失败(需修复后重试)| ⏸️=暂停(等待用户确认)
## 代办清单({连续/步进}模式)
| # | 步骤 | 执行方式 | 预期输出 | 组 | 状态 |
|---|------|----------|----------|-----|------|
| 1 | 子模块端口收集 | 内联(Read) | 端口汇总表 | A | ⬜ |
| 2 | 接口一致性检查 | 内联(检查) | 冲突清单 | A | ⬜ |
| 3 | 顶层模块编写 | 内联(Write) | `{module}_top.v` | B | ⬜ |
| 4 | 连接图生成 | Skill:chip-png-d2-gen | `wd_{module}_top_connect.png` | B | ⬜ |
| 5 | 系统级 Lint | Bash:verilator | lint 报告(0 Error) | C | ⬜ |
| 6 | 集成验证 | 内联(检查) | 集成检查清单 | C | ⬜ |
关键门禁:
- Step 2 接口:冲突数 = 0,否则暂停确认
- Step 5 Lint:0 Error,否则自愈修复
- Step 6 集成:7/7 检查项通过
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 12d ago First seen · 357 lines · 205 tokens per session scan A 0d6db2d523c0
chip-top-integrator is an agent published in the GitHub repository zhaixin244-wq/fnw (29 stars, last pushed 3mo ago), licensed MIT. It adds 205 tokens to every session and 4,001 once invoked, about $0.0010 per session on Opus 5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-30.
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