Getting it into your agent
One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.
git clone --depth 1 https://github.com/HermeticOrmus/LibreEmbed-Claude-CodeWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/commands/hermeticormus/libreembed-claude-code/fpga)<a href="https://agentmods.dev/commands/hermeticormus/libreembed-claude-code/fpga"><img src="https://agentmods.dev/badge/commands/hermeticormus/libreembed-claude-code/fpga/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/commands/hermeticormus/libreembed-claude-code/fpga"><img src="https://agentmods.dev/badge/commands/hermeticormus/libreembed-claude-code/fpga.svg" alt="Reviewed on agentmods" width="80" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00025 | $0.00833 |
| Opus 5.5 | $0.00010 | $0.00333 |
| Sonnet 5.5 | $0.00005 | $0.00167 |
| Haiku 4.5 | $0.00003 | $0.00083 |
Grade A, and why
fpga scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 15d ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 101 lines — stays where its author put it; the contents beside it link to each section on GitHub.
/fpga
FPGA integration command: HDL generation, synthesis, programming, MCU interface.
Trigger
/fpga <action> [options]
Actions
design
Generate a Verilog module for a specified function.
/fpga design --module axi-lite-slave --regs 8 --data-width 32
/fpga design --module spi-slave --mode 0 --bits 8
/fpga design --module pwm --channels 4 --resolution 16
/fpga design --module uart --baud 115200 --clk 100MHz
synthesize
Generate synthesis Tcl script for Vivado or Quartus.
/fpga synthesize --tool vivado --part xc7a35tcpg236-1 --top my_top
/fpga synthesize --tool quartus --device 5CEBA4F23C7 --top my_top
program
Generate programming commands.
/fpga program --tool vivado --interface jtag --bitfile my_top.bit
/fpga program --tool openocd --interface jlink --bitfile my_top.svf
/fpga program --tool quartus-pgm --interface usb-blaster
interface
Generate MCU-side driver code for the FPGA interface.
/fpga interface --type spi --mcu stm32f407 --fpga-regs 8
/fpga interface --type axi-lite --mcu zynq --base-addr 0x43C00000
Process
- Define register map (address, name, R/W, reset value) before writing HDL.
- Write Verilog with non-blocking assignments in clocked always blocks.
- Write a testbench and simulate with Icarus Verilog or Vivado Simulator.
- Add timing constraints for all clocks and CDC paths.
- Run implementation, check timing report (worst negative slack must be positive).
Output Examples
Register map definition
Offset | Name | Access | Bits | Description
0x00 | CTRL | R/W | [0] | Enable (1=on)
[1] | Reset (self-clearing)
0x04 | PERIOD | R/W | [15:0]| PWM period in clock cycles
0x08 | DUTY | R/W | [15:0]| PWM duty cycle count
0x0C | STATUS | RO | [0] | Output active
[7:4] | Error flags
Icarus Verilog simulation
# Compile
iverilog -o sim.vvp tb_spi_slave.v spi_slave.v
# Run
vvp sim.vvp
# Waveform (requires GTKWave)
vvp sim.vvp -lxt2
gtkwave sim.lxt
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 15d ago First seen · 101 lines · 25 tokens per session scan A fe670d91e0fe
fpga is a command published in the GitHub repository HermeticOrmus/LibreEmbed-Claude-Code (50 stars, last pushed 6d ago), licensed MIT. It adds 25 tokens to every session and 833 once invoked, about $0.0001 per session on Opus 5.5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-10-01.
Other commands, from other repositories
debug
A command-line debugging toolkit for embedded programs using J-Link or OpenOCD, tools that connect a computer to a microcontroller for inspection.
la
A command for capturing and decoding signals with a Saleae logic analyzer, a device that records electrical digital signals over time. It supports buses such as UART, SPI, and I2C, which are common ways chips communicate with peripherals.
flash
A command for writing firmware to a microcontroller using OpenOCD, a tool that programs chips through a connected debugging probe.
test
A command for generating and running tests for embedded C code, either on a computer or on a physical development board. It creates both runnable test code and a written list of test cases.
map
A parser for Keil compiler map files, which are build reports describing where program code and data are placed in memory. It reports object sizes, memory regions, symbols, and stack or heap details.
verify
An embedded-device verification workflow that checks a development step through building, flashing firmware, debugging with J-Link, and reading serial logs. Firmware is software that runs directly on a microcontroller or other device.