quartus91-vhdl-flow

Quartus II 9.1 VHDL Flow

Purpose

Use this skill to take a digital design request from VHDL source through a usable Quartus II 9.1 project: create or update source files, create the project, apply board pins, generate .vwf stimulus from the user's simulation requirements, run simulation or compile checks, inspect reports, and optionally program hardware.

Prefer the local quartus91 MCP tools whenever they are available. The MCP server normally gets its Quartus path from QUARTUS91_ROOT in the MCP client config.

• Default board preset: maxii_epm1270t144c5_lab
• Typical server entry point: <cloned-repo>\src\server.js

If the active tool schema does not expose a newer MCP tool such as quartus_list_board_presets, quartus_set_pins, or boardPreset/resourceBindings, inspect the cloned quartus91-mcp\src\server.js if available and use direct locationAssignments as a fallback. The user may need to restart Codex after installing or updating the MCP server.

Load References

• Read references/maxii-board-preset.md before selecting board modules, resolving pin conflicts, or expanding resourceBindings.
• Read references/mcp-workflows.md when you need exact tool-call shapes for project creation, VWF generation, pin locking, simulation, compile, or programming.

End-To-End Workflow

1. Determine the project shape. Use the user's requested top entity, files, board modules, reset polarity, clock period, and simulation duration. If details are missing and low risk, choose conservative defaults: VHDL top entity equals project name, clk on the board clock, active-high reset unless the source names rst_n, nanosecond VWF units, and functional simulation before full compile.
2. Write or edit VHDL source. Keep Quartus II 9.1 compatibility: use VHDL-93 style constructs, ieee.std_logic_1164, ieee.numeric_std, explicit widths, simple file/entity names, and avoid VHDL-2008-only features unless the user explicitly requires them.
3. Create or update the project. Use quartus_create_project with projectDir, projectName, revision, topLevelEntity, source files, and either boardPreset: "maxii_epm1270t144c5_lab" plus resourceBindings, or direct family/device/locationAssignments when the preset tool is unavailable.
4. Lock pins. Prefer resourceBindings for board modules (clock, reset, leds, switches, seven_segment_digits, lcd12864, etc.). Check shared pins before binding VGA, LEDs, I2C devices, or alternate seven-segment mappings.
5. Generate VWF. Translate the user's natural-language simulation request into structured signals, clocks, pulses, events, sequences, and waveforms; then call quartus_generate_vwf with attachToProject: true.
6. Simulate. Start with quartus_simulate_vwf using dryRun: true when paths or generated vectors are uncertain; then run functional simulation. Use timing simulation only after a successful compile or when the user specifically asks for post-fit timing behavior.
7. Compile and inspect. Use quartus_run_flow for full compile, or quartus_run_stage for targeted stages. Then use quartus_read_report and report errors, important warnings, selected device, top entity, fitted pins, and output files.
8. Program only on explicit user intent. Call quartus_list_hardware first; then use quartus_program_device, preferably with dryRun: true before actual programming.