rtl-specification-consistency-checker

RTL-Specification Consistency Checker

Overview

This skill enables systematic checking of behavioral consistency between high-level hardware specifications and RTL implementations. It extracts requirements from specifications, maps them to RTL logic, and classifies each requirement as satisfied, violated, underspecified, or uncheckable.

Consistency Checking Workflow

Follow this sequential process to check RTL-specification consistency:

1. Parse and Understand Inputs

Read and analyze both the specification and RTL code:

Specification Analysis:

• Identify the format (natural language, tables, timing diagrams, protocol rules)
• Extract all behavioral requirements
• Note any assumptions or constraints
• Identify ambiguous or incomplete sections

RTL Analysis:

• Identify the HDL language (Verilog, VHDL, SystemVerilog)
• Locate key modules and their interfaces
• Identify state machines, registers, and control logic
• Note clock domains and reset strategies

2. Extract Behavioral Requirements

Formalize each requirement from the specification:

Requirement Types:

Functional Requirements:

• Input-output relationships
• State transitions
• Data transformations
• Protocol sequences

Timing Requirements:

• Setup/hold times
• Latency constraints
• Throughput requirements
• Clock cycle counts

Safety Properties:

• Invariants that must always hold
• Forbidden states or transitions
• Mutual exclusion constraints
• Data integrity conditions

Liveness Properties:

• Progress guarantees
• Eventual responses
• Fairness conditions

For each requirement, document:

• Requirement ID
• Description in natural language
• Formalized property (if possible)
• Source location in specification
• Priority/criticality

3. Map Requirements to RTL

Identify RTL constructs corresponding to each requirement:

Signal Mapping:

• Map specification signals to RTL signals
• Identify relevant registers and wires
• Note signal widths and types

Logic Mapping:

• Identify modules implementing each requirement
• Locate state machines and control logic
• Find combinational and sequential logic blocks
• Note line numbers and code locations