Getting it into your agent
One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.
npx skills add bahaabdelwahed/embedded-claude-plugin --skill memory-bus-architecturegit clone --depth 1 https://github.com/bahaabdelwahed/embedded-claude-pluginWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/skills/bahaabdelwahed/embedded-claude-plugin/memory-bus-architecture)<a href="https://agentmods.dev/skills/bahaabdelwahed/embedded-claude-plugin/memory-bus-architecture"><img src="https://agentmods.dev/badge/skills/bahaabdelwahed/embedded-claude-plugin/memory-bus-architecture/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/skills/bahaabdelwahed/embedded-claude-plugin/memory-bus-architecture"><img src="https://agentmods.dev/badge/skills/bahaabdelwahed/embedded-claude-plugin/memory-bus-architecture.svg" alt="Reviewed on agentmods" width="80" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00095 | $0.01260 |
| Opus 5 | $0.00048 | $0.00630 |
| Sonnet 5 | $0.00019 | $0.00252 |
| Haiku 4.5 | $0.00010 | $0.00126 |
Grade A, and why
memory-bus-architecture scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 9d ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 106 lines — stays where its author put it; the contents beside it link to each section on GitHub.
Memory and Bus Architecture Extraction
Extract and interpret STM32 bus architecture, memory organization, and clock tree configuration from user-provided reference manual PDFs.
What to Extract
Bus Architecture
- Bus matrix connections (which masters connect to which slaves)
- AHB buses: AHB1, AHB2, AHB3 (and which peripherals are on each)
- APB buses: APB1 (low-speed), APB2 (high-speed) and their max frequencies
- Cortex-M buses: I-Bus (instruction), D-Bus (data), S-Bus (system)
- Bus arbitration: round-robin vs fixed priority
DMA Architecture
- DMA controller count (DMA1, DMA2)
- Streams/channels per controller
- DMA request mapping: which peripheral is on which stream/channel
- DMA bus connections: which DMA can access which memory/peripheral
- FIFO configuration options
Clock Tree
- Clock sources: HSI, HSE, LSI, LSE, MSI (if applicable)
- PLL configuration: input source, multiplication/division factors
- SYSCLK source selection
- AHB prescaler (HCLK)
- APB1 prescaler (PCLK1) and APB2 prescaler (PCLK2)
- Peripheral clock sources and maximum frequencies
- MCO (Microcontroller Clock Output) options
Where to Find This Information
Reference Manual - Bus Architecture
Glob pattern: docs/reference-manual/*.pdf
- Read pages 1-5 (table of contents)
- Find chapter titled "System and memory overview" or "Memory and bus architecture" (typically chapter 2)
- Read that chapter (usually 10-20 pages) to find:
- System architecture block diagram (bus matrix figure)
- Bus matrix table showing master/slave connections
- Memory map table with address ranges
- Find chapter titled "DMA controller" or "DMA"
- DMA request mapping table (critical: shows which peripheral maps to which stream/channel)
- DMA block diagram showing bus connections
Reference Manual - Clock Tree
- From ToC, find chapter titled "Reset and clock control (RCC)"
- Read the clock tree figure (usually one of the first figures in the RCC chapter)
- Extract PLL configuration registers and prescaler options
- Find the table showing maximum frequencies per bus domain
What ships with it
1 file beside SKILL.md in the same directory: the scripts, references and assets a skill reads on demand. Not counted in the per-session cost; read them before you install if any of them is executable.
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 9d ago First seen · 106 lines · 95 tokens per session scan A ab5b2c810137
memory-bus-architecture is a skill published in the GitHub repository bahaabdelwahed/embedded-claude-plugin (5 stars, last pushed 5mo ago), licensed MIT. It adds 95 tokens to every session and 1,260 once invoked, about $0.0005 per session on Opus 5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-31.
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