AI-powered SystemVerilog development assistant — design, verify, debug, and deliver working RTL with natural language.
Skill Claude CodeCodex
Codebase architect - Maps and documents SystemVerilog projects. This skill should be used when the user wants to understand a codebase structure, generate architecture documentation, or onboard to a new RTL project. Example requests: "map this codebase", "document the architecture", "show module hierarchy".
Skill Claude CodeCodex
Parallel build orchestrator for SystemVerilog creation tasks. Decomposes designs into independent modules, builds in parallel phases, runs verification on each component, then integrates. Example: "/gf-build RISC-V CPU with ALU, regfile, decoder, control FSM".
Skill Claude CodeCodex
Python-based testbench generation using Cocotb. Alternative to SystemVerilog testbenches for Python-native hardware engineers. Example: "create a cocotb test for the FIFO", "write Python testbench".
Skill Claude CodeCodex
Error translation layer for hardware tool outputs. Converts cryptic Verilator, Yosys, GHDL, and simulation errors into 3-layer explanations. Used internally by gf orchestrator — not user-invocable directly.
Skill Claude CodeCodex
Expand mode - asks clarifying questions, presents options with trade-offs, then hands off to appropriate skill/agent with enriched context.
Skill Claude CodeCodex
Formal verification from natural language. Generates SVA properties, configures SymbiYosys, runs proofs, and explains results. Example: "formally verify the FIFO never overflows".
Skill Claude CodeCodex
FuseSoC build system integration for GateFlow. Generates .core files and drives synthesis/simulation through Edalize backends (Vivado, Quartus, open-source tools). Use when the user needs to create a FuseSoC core file, build with Edalize, or integrate RTL into a FuseSoC project.
Skill Claude CodeCodex
Auto-detect IP blocks within FPGA and hardware codebases. Scans for module instantiations, identifies missing implementations, matches standard IP patterns, and dispatches agents to fill gaps. Example: "scan for missing IP blocks", "detect what needs implementing", "find unimplemented modules", "auto-fill IP blocks".
Skill Claude CodeCodex
IP block library manager. Install, list, and query verified drop-in hardware components. Each block includes RTL, testbench, formal properties, and documentation. Example: "add a FIFO to my project", "/gf-ip add uart".
Skill Claude CodeCodex
Contextual learning — micro-lessons embedded in workflow output. Explains hardware concepts on first encounter, tracks what has been taught, generates practice exercises on demand. Used internally by orchestrator — not typically invoked directly.
Skill Claude CodeCodex
SystemVerilog learning mode — generates exercises, reviews solutions, and teaches RTL design patterns. Use when the user wants to learn SystemVerilog, practice hardware design, get exercises, or understand verification methodology.
Skill Claude CodeCodex
SystemVerilog lint checker with structured output for orchestration. Runs Verilator lint, categorizes errors/warnings, explains issues, and returns a parseable result block for /gf orchestration.
Skill Claude CodeCodex
KiCad schematic and PCB generation from natural language. AI-verified drafts with DRC/ERC/AI review loop. Example: "design a breakout board for iCE40 with SPI flash and 2 PMODs".
Skill Claude CodeCodex
Board-aware pin mapping. Generates FPGA constraint files (.xdc/.pcf/.lpf/.cst) with correct pin assignments, I/O standards, and drive strength for target boards. Example: "map SPI to PMOD JA on Arty A7", "generate constraints for my iCEBreaker".