Getting it into your agent
One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.
npx skills add ddddjaak/se-skills --skill hardware-architecture-designgit clone --depth 1 https://github.com/ddddjaak/se-skillsWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/skills/ddddjaak/se-skills/hardware-architecture-design)<a href="https://agentmods.dev/skills/ddddjaak/se-skills/hardware-architecture-design"><img src="https://agentmods.dev/badge/skills/ddddjaak/se-skills/hardware-architecture-design/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/skills/ddddjaak/se-skills/hardware-architecture-design"><img src="https://agentmods.dev/badge/skills/ddddjaak/se-skills/hardware-architecture-design.svg" alt="Reviewed on agentmods" width="80" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00139 | $0.05077 |
| Opus 5 | $0.00069 | $0.02538 |
| Sonnet 5 | $0.00028 | $0.01015 |
| Haiku 4.5 | $0.00014 | $0.00508 |
Grade A, and why
hardware-architecture-design scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 12d ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 320 lines — stays where its author put it; the contents beside it link to each section on GitHub.
Hardware Architecture Design
Overview
System architecture says how modules interact. Hardware architecture says what the PCB looks like to make those interactions physically real — decomposing the system into power domains, assigning every pin, defining every voltage rail, analyzing signal integrity, selecting critical components, and documenting the PCB constraints the layout engineer needs.
A good hardware architecture document answers every question a PCB designer will ask: "what voltage does this rail need?", "which pins connect to which?", "what trace impedance must this differential pair maintain?", "why did we choose this PMIC over that one?". Without it, board bring-up becomes a debugging marathon instead of a verification checklist.
Hardware architecture design is the hardware counterpart to architecture-design — where that skill decomposes into software modules and message-passing interfaces, this skill decomposes into power domains, physical interconnects, and electrical constraints.
When to Use
- Structured system requirements exist (output of
requirements-decompose), HW-domain confirmed - System architecture exists (output of
architecture-design), module/block decomposition defined - Starting a new board or board revision from scratch
- Adding a major hardware subsystem (new power domain, high-speed interface, sensor array)
- Evaluating component alternatives against quantified electrical and thermal requirements
- A design review surfaces pin-assignment conflicts, power sequencing gaps, or SI concerns
When NOT to use:
- Requirements not yet decomposed (run
requirements-decomposefirst) or system architecture not yet defined (runarchitecture-designfirst) - Single component swap with identical footprint/electrical — no architecture impact
- Pure PCB layout task or existing architecture doc needing only minor clarification
- Purely software/firmware with no hardware design impact
Context Boundary
Read ONLY:
- System architecture document (module decomposition, interface definitions)
- HW-domain system requirements (power, thermal, mechanical, EMC, SI, reliability)
- Chip datasheets, reference manuals, application notes for MCU/SoC
- Industry standards referenced by requirements (PCIe CEM, USB-IF, DDR JEDEC)
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 12d ago First seen · 320 lines · 139 tokens per session scan A 1c62817cf64e
hardware-architecture-design is a skill published in the GitHub repository ddddjaak/se-skills (4 stars, last pushed 1mo ago), licensed MIT. It adds 139 tokens to every session and 5,077 once invoked, about $0.0007 per session on Opus 5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-31.
Other skills, from other repositories
gke-compute-classes
Configures, optimizes, and troubleshoots GKE ComputeClasses. Use when configuring Spot VMs with on-demand fallback, targeting specific accelerators (GPUs/TPUs) or machine families, restricting ComputeClass access, or debugging pending pods related to node pool auto-creation. Do not use for cluster-level Node Auto…
jetson-diagnostic
Read-only Jetson health snapshot for identity, memory, GPU, thermal, power, storage, services, and top processes.
doca-socket-relay
Use this skill when the operator is driving the DOCA Socket Relay to bridge a socket-oriented host application onto a BlueField DPU peer without rewriting it — picking the deployment shape (in-process, sidecar, or BlueField service container), configuring the host-side socket and the DPU-side forwarding endpoint…
offensive-z-wave
Z-Wave attack methodology — sniffing with Z-Force / EZ-Wave / RTL-SDR + ZniffMobile, S0 (legacy) network-key derivation flaw and key reuse, S2 (modern) ECDH commissioning analysis, replay/injection on unauthenticated nodes, default-key brute-force on test deployments, and home-automation hub pivots. Use when targeting…
hsb-flash
Flash the FPGA on an HSB board connected to an NVIDIA devkit. Supports HSB Lattice boards (FPGA versions 2407, 2412, 2507, 2510) and Leopard Imaging VB1940 "all-in-one" cameras (FPGA versions 2507, 2510). Uses release-specific YAML manifests and board-type-specific program commands. Lattice and VB1940 commands must…
jetson-validate-image
Use after jetson-flash-image to run static BSP checks, on-target smoke/regression tests on a flashed DUT, or both. Not for build or flash steps. Triggers: validate bsp, on-target validation.