Getting it into your agent
One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.
npx skills add ddddjaak/se-skills --skill hardware-detailed-designgit clone --depth 1 https://github.com/ddddjaak/se-skillsWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/skills/ddddjaak/se-skills/hardware-detailed-design)<a href="https://agentmods.dev/skills/ddddjaak/se-skills/hardware-detailed-design"><img src="https://agentmods.dev/badge/skills/ddddjaak/se-skills/hardware-detailed-design/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/skills/ddddjaak/se-skills/hardware-detailed-design"><img src="https://agentmods.dev/badge/skills/ddddjaak/se-skills/hardware-detailed-design.svg" alt="Reviewed on agentmods" width="80" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00127 | $0.05763 |
| Opus 5 | $0.00063 | $0.02882 |
| Sonnet 5 | $0.00025 | $0.01153 |
| Haiku 4.5 | $0.00013 | $0.00576 |
Grade A, and why
hardware-detailed-design scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 11d ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 336 lines — stays where its author put it; the contents beside it link to each section on GitHub.
Hardware Detailed Design
Overview
Hardware architecture says which pin connects to what. Hardware detailed design says exactly how — the trace width, the decoupling capacitor value, the ground plane stitching pattern, the maximum via count per net. This is the contract between the SE/architect and the PCB designer: constraints that are specified prevent re-spins; constraints that are assumed cause them.
This skill transforms the hardware architecture document into a detailed hardware design that an EE can take directly into schematic capture and PCB layout. Every constraint is quantified. Every tolerance is specified. If the chip datasheet does not provide a parameter, this skill flags it rather than inferring it.
When to Use
- Hardware architecture is confirmed and schematic capture is about to begin
- Preparing PCB layout constraints for a new board design
- The EE team needs formal design rules before starting layout
- A design review found that hardware constraints were underspecified
- Adding a new subsystem (power domain, high-speed interface) to an existing design
When NOT to use:
- Hardware architecture is not yet designed (run
hardware-architecture-designfirst) - The change is a single component value tweak with no architecture impact
- Pure software design (use
software-detailed-design) - Algorithm design (use
algorithm-design)
Context Boundary
Read ONLY:
- Hardware architecture document (pin assignments, voltage domains, component selection, constraint analysis)
- Component datasheets for parts selected in the hardware architecture
- Industry standards referenced by constraints (IPC-2221 for trace width, JEDEC for memory routing, PCIe CEM for connector specs)
Do NOT read: software architecture, firmware design, test plans, or requirements documents. If a design rule requires software input (e.g., "which GPIOs need debug header access?"), surface an Open Item — do not read the software architecture to answer it.
If the chip datasheet does not provide a required parameter, flag it rather than inferring it. A missing datasheet parameter is an Open Item, not a gap you fill with experience.
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 11d ago First seen · 336 lines · 127 tokens per session scan A 7e2617b2eeec
hardware-detailed-design is a skill published in the GitHub repository ddddjaak/se-skills (4 stars, last pushed 1mo ago), licensed MIT. It adds 127 tokens to every session and 5,763 once invoked, about $0.0006 per session on Opus 5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-31.
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