mcp_diptrace: Skill for Claude Code

DipTrace Board Build Pipeline

The One Rule

build_schematic_document() / build_pcb_document() produce XML that DipTrace 5.3 CANNOT parse (silent hang). Every generated file MUST pass through nativeization before opening in the editor.

Architecture Overview

Phase 0: SOURCE          LCSC/EasyEDA → vendor/*.json → *.elixml
Phase 1: CONNECTIVITY    Builder class → PlacePart + ConnectPins
Phase 2: VISUAL WIRING   Ground symbols, Net Ports, Wires, Labels
Phase 3: NATIVEIZE       Transplant content → native template → opens in DipTrace
Phase 4: PCB SYNC        build_sync_plan → ComponentSyncMapping → placement
Phase 5: ROUTING         Priority batches → plan_pcb_routes → AddTraceOperation
Phase 6: FINISH          Pours + stitching → sanitize pads → silkscreen
Phase 7: VERIFY          ERC/DRC → SVG preview → native gate11

Phase 0: Source Components

Resolution order (house rule)

1. DipTrace installed catalog (query_builtin_library_catalog)
2. LCSC/EasyEDA exact MPN match
3. Custom-drawn only after both documented zero matches

LCSC fetch pattern

from diptrace_mcp.pipeline import lcsc_fetch
result = lcsc_fetch("ESP32-S3-MINI-1U-N8", "vendor/")
# Returns: code, mpn, package, pins, pads, json_path, datasheet_path

Fallback chain for MPN→C-code resolution:

1. DuckDuckGo HTML scrape: html.duckduckgo.com/html/?q=<MPN>+lcsc
2. JLCPCB parts API: POST selectSmtComponentList
3. Manual web search

JSON → .elixml conversion rules

EasyEDA geometry:

• Units are 10 mil (0.254 mm); Y grows UP; DipTrace Y grows DOWN
• Symbol pins: P~show~0~<number>~<x>~<y>~<rotation>~<id>
• Pin names: scan ^^ sections, find <value>~start/end~~~#color
• Body rect: R~<x>~<y>~...~<w>~<h> or synthesize from PL/PG bbox
• Footprint pads: PAD~<shape>~x~y~w~h~layer~net~number~hole_r~points~angle
  • Shape ∈ {RECT, POLYGON, OVAL, ELLIPSE, CIRCLE}; POLY = use declared w/h
• Silk tracks: TRACK~<width>~<layer>~<net>~points

Critical transforms:

• Pad ordering: DipTrace sync maps pins↔pads POSITIONALLY. Pattern pads MUST be sorted to match symbol pin sequence exactly.
• Merged pads: "A1B12" covers two connector legs. Either split into two half-width pads OR renumber to integers with alias JSON.
• Duplicate pad numbers (ESP32 thermal grid "61"×9): merge into one pad with union bounding box.
• Alphanumeric pad numbers: DipTrace sync resolves by numeric Id fallback; renumber all non-digit pads sequentially in pin order + save alias map.
• Zero-length pins: nearest-edge body synthesis can produce length=0; clamp to ≥0.5mm.
• ElectricType: valid values are Input, Output, Bidirectional, Power, Passive. Unknown values may hang Schematic.exe.