fpga-patterns

fpga-patterns

Knowledge Base

Synthesizable Verilog patterns for FPGA-MCU integration. Targeting Xilinx Artix-7 and Intel Cyclone V.

---

Pattern 1: Register Bank with Read/Write Strobe

Simpler than AXI-Lite for SPI-connected FPGAs:

/* 8 x 32-bit register file with address/data/write-enable interface */
module reg_bank (
    input  wire        clk,
    input  wire        rst_n,
    input  wire [2:0]  addr,
    input  wire [31:0] wdata,
    input  wire        wen,
    output reg  [31:0] rdata,
    /* Application outputs */
    output wire [31:0] reg0_out,
    output wire [31:0] reg1_out,
    input  wire [31:0] reg4_in,   /* Read-back from hardware */
    input  wire [31:0] reg5_in
);
    reg [31:0] regs [0:7];

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            regs[0] <= 32'h0; regs[1] <= 32'h0;
            regs[2] <= 32'h0; regs[3] <= 32'h0;
        end else if (wen) begin
            regs[addr] <= wdata;
        end
    end

    /* Read: hardware status registers override software writes */
    always @(*) begin
        case (addr)
            3'd4:    rdata = reg4_in;
            3'd5:    rdata = reg5_in;
            default: rdata = regs[addr];
        endcase
    end

    assign reg0_out = regs[0];
    assign reg1_out = regs[1];
endmodule

---

Pattern 2: Clock Domain Crossing — 2FF Synchronizer

Signals crossing from one clock domain to another must be synchronized to avoid metastability.

/* 2-flipflop synchronizer for a single control bit */
module sync_2ff (
    input  wire dst_clk,
    input  wire rst_n,
    input  wire sig_in,      /* Asynchronous input */
    output reg  sig_out      /* Synchronized output */
);
    reg ff1;

    (* ASYNC_REG = "TRUE" *) reg sync_ff1;   /* Vivado: keep close in placement */
    (* ASYNC_REG = "TRUE" *) reg sync_ff2;

    always @(posedge dst_clk or negedge rst_n) begin
        if (!rst_n) begin
            sync_ff1 <= 0; sync_ff2 <= 0;
        end else begin
            sync_ff1 <= sig_in;
            sync_ff2 <= sync_ff1;
        end
    end
    assign sig_out = sync_ff2;
endmodule