apple-silicon

Apple Silicon

Purpose

Guide agents through Apple Silicon (M-series) development: unified memory architecture, AMX matrix coprocessor access via Accelerate, Metal Performance Shaders for GPU compute, sysctl hardware queries, Instruments profiling, command-line leak tools, Rosetta 2 translation behavior, and 16KB page size implications.

When to Use

• Optimizing native ARM64 apps on macOS for M1/M2/M3/M4
• Using GPU/NPU compute without discrete GPU PCIe transfers
• Profiling memory and CPU with Instruments or command-line tools
• Understanding Rosetta 2 compatibility for x86 binaries
• Adapting code for 16KB page size on Apple Silicon
• Accessing matrix acceleration via Accelerate/vDSP/BLAS

Workflow

1. Unified memory architecture

Apple Silicon SoC
├── CPU cores (P + E cores)
├── GPU cores
├── Neural Engine (NPU)
└── Unified DRAM — single address space, no PCIe copy

Implications:

• cudaMemcpy equivalent is unnecessary for CPU↔GPU on Metal
• Memory bandwidth shared across agents — profile holistically
• Process memory includes all unified allocations

2. Hardware information

# CPU and chip info
sysctl -n machdep.cpu.brand_string
sysctl hw.physicalcpu hw.logicalcpu
sysctl hw.memsize

# ARM64 features (keys vary by chip — grep if specific FEAT_* is missing)
sysctl -a hw.optional.arm 2>/dev/null | grep -iE 'sve|bf16|mte'

# Cache line size
sysctl hw.cachelinesize

# Page size (16KB on macOS Apple Silicon)
sysctl hw.pagesize    # 16384
getconf PAGESIZE

3. 16KB page size considerations

macOS on Apple Silicon uses 16KB pages (not 4KB):

// Align hot buffers to page size
size_t page = sysconf(_SC_PAGESIZE);  // 16384
void *buf = aligned_alloc(page, size);

// mmap alignment must be page-aligned
mmap(NULL, size, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0);

Impact:

• posix_memalign minimum alignment often 16KB for large allocs
• JVM/Go runtimes auto-tune; custom allocators must adapt
• Test on device — x86 CI may use 4KB pages