Skill Codex
Use pyslang-mcp for compiler-backed Verilog and SystemVerilog context. Trigger this skill for RTL, HDL, Verilog, SystemVerilog, module, interface, package, .sv, .svh, .v, .vh, or .f filelist analysis, review, debugging, coding, refactoring, hierarchy inspection, diagnostics triage, symbol lookup, include/define…
not rated 22
+1 4mo ago A 107 tokens
original Apache-2.0