Plugin Claude Code
hdldiagZero - JSON-spec-driven SVG block diagrams of HDL/RTL designs.
19 22d ago A
tokens not measured
original MIT
hdldiagzero
02Plugin Claude Code
Generate clean SVG block diagrams of HDL/RTL/SoC designs. Color-codes by clock domain, distinguishes AXI-MM/Lite/Stream, draws CDC blocks with split fill, omits clock/reset/JTAG/debug clutter, and validates output geometry.
19 22d ago A
tokens not measured
original MIT
hdldiagzero
03Skill Claude CodeCodex
Generate validated SVG block diagrams for HDL/RTL/FPGA/SoC designs. Use when asked to draw, diagram, sketch, render, or visualize Verilog, SystemVerilog, VHDL, Vivado BD, or LiteX architecture. Produces JSON specs plus SVGs, color-codes clock domains, distinguishes AXI/MM/Lite/Stream and TileLink, and hides…
19 22d ago A 93 tokens
original MIT