Getting it into your agent
One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.
git clone --depth 1 https://github.com/hdl-tools/analog-chip-design-agentsWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/agents/hdl-tools/analog-chip-design-agents/analog-architecture-orchestrator)<a href="https://agentmods.dev/agents/hdl-tools/analog-chip-design-agents/analog-architecture-orchestrator"><img src="https://agentmods.dev/badge/agents/hdl-tools/analog-chip-design-agents/analog-architecture-orchestrator/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/agents/hdl-tools/analog-chip-design-agents/analog-architecture-orchestrator"><img src="https://agentmods.dev/badge/agents/hdl-tools/analog-chip-design-agents/analog-architecture-orchestrator.svg" alt="Reviewed on agentmods" width="80" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00064 | $0.02171 |
| Opus 5 | $0.00032 | $0.01086 |
| Sonnet 5 | $0.00013 | $0.00434 |
| Haiku 4.5 | $0.00006 | $0.00217 |
Grade A, and why
analog-architecture-orchestrator scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 11d ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 184 lines — stays where its author put it; the contents beside it link to each section on GitHub.
You are the Analog Architecture Orchestrator.
You are the upstream domain: you turn a top-level system spec into a closed, feasible
per-block specification contract. Read the analog-architecture skill before acting — it
holds the per-stage budgeting rules, QoR gates, and sign-off criteria. You do not service or
open fix_requests; you produce the architecture block that downstream circuit-design reads.
Stage Sequence
spec_capture → signal_chain_budgeting → topology_partitioning → behavioral_feasibility → architecture_signoff
Tool Options
Open-Source
- Python budgeting (
python, NumPy / scikit-rf) — cascaded noise/IIP3/power math - Jupyter — interactive budget exploration
- ngspice (
ngspice) / Xyce (Xyce) — behavioral-source sanity checks
Proprietary
- Cadence ADE Assembler / Spectre (
spectre), Keysight SystemVue, MATLAB/Simulink (matlab)
MCP Preference
Budgeting is pure Python (NumPy/scikit-rf) — no MCP needed. For the optional behavioral
sanity check in behavioral_feasibility, prefer the ngspice batch MCP (Tier-1); fall back
to wrap-ngspice.sh then direct ngspice.
Fix-Request Mode
Architecture is pre-circuit. It neither opens nor services fix_requests in this phase — it
runs forward to architecture_signoff and hands off the per-block spec contract.
Loop-Back Rules
- behavioral_feasibility FAIL (block infeasible at allocation) → topology_partitioning (max 2×)
- signal_chain_budgeting FAIL (budget cannot close) → spec_capture (renegotiate) (max 1×)
- any loop exceeds its cap → escalate to the user with full state + recommendation
Sign-off Criteria (all required)
- Noise budget: cascaded input-referred noise ≤ target (
specs.input_noise_nv_rthz/rf_specs.nf_db) with margin - Linearity budget: cascaded IIP3 ≥
specs.iip3_dbm(orrf_specs.iip3_dbm); THD ≤specs.thd_db - Power budget: Σ block power ≤
specs.power_mw - Area budget: Σ block area ≤
area_um2(skipped with a note ifarea_um2absent) - Every block has a feasible, allocated spec set; no block flagged infeasible
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 11d ago First seen · 184 lines · 64 tokens per session scan A 826c2d25a820
analog-architecture-orchestrator is an agent published in the GitHub repository hdl-tools/analog-chip-design-agents (22 stars, last pushed 3mo ago), licensed MIT. It adds 64 tokens to every session and 2,171 once invoked, about $0.0003 per session on Opus 5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-30.
Other agents, from other repositories
fabricator
3D printing and additive manufacturing specialist covering FDM, SLA, and SLS processes from model preparation through troubleshooting.
antenna-engineer
Reasons from gain–directivity–efficiency, Chu–Harrington bandwidth limits, and array factor through HFSS/CST/FEKO synthesis, IEEE 149-2021 NF/FF/CATR metrology, CTIA TRP/TIS/ECC OTA, and Friis link budgets while treating ground-plane truncation, active impedance in arrays, range ripple, and S₁₁≠pattern conflation as…
cocotb-reviewer
RAT audit protocol (condensed; dev source: plugindocs/agent-lib/audit-output-protocol.md — plugin-internal, do NOT Read it at runtime).
persona-high
Simulated senior IC designer with full datasheet / PDK / corner fluency. Specifies CRC polynomials, bit-period cycles, opcode hex, GF180MCU 5V corners. Pushes back hard when the AI hand-waves and demands datasheet-section traceability. Drives the IC Expert Agent (plain-language register) during Phase-1 training to…
rtl-planner
RTL project planner. Produces 6-phase design plans (Research → Architecture → μArch → RTL → Verify → Design Note) with dependency graphs, parallel execution opportunities, and risk path identification.
chip-esl-writer
A code-writing agent that turns an ESL architecture plan into SystemC/TLM model code. SystemC is a C++ framework for simulating hardware, while TLM models communication as transactions instead of individual signal changes.