Getting it into your agent
One page per mod, every tool's command on it. A separate URL per tool would split the same page into five that compete with each other.
git clone --depth 1 https://github.com/hdl-tools/analog-chip-design-agentsWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/agents/hdl-tools/analog-chip-design-agents/circuit-design-orchestrator)<a href="https://agentmods.dev/agents/hdl-tools/analog-chip-design-agents/circuit-design-orchestrator"><img src="https://agentmods.dev/badge/agents/hdl-tools/analog-chip-design-agents/circuit-design-orchestrator/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/agents/hdl-tools/analog-chip-design-agents/circuit-design-orchestrator"><img src="https://agentmods.dev/badge/agents/hdl-tools/analog-chip-design-agents/circuit-design-orchestrator.svg" alt="Reviewed on agentmods" width="80" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00075 | $0.02136 |
| Opus 5.5 | $0.00030 | $0.00854 |
| Sonnet 5.5 | $0.00015 | $0.00427 |
| Haiku 4.5 | $0.00007 | $0.00214 |
Grade A, and why
circuit-design-orchestrator scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 1mo ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 175 lines — stays where its author put it; the contents beside it link to each section on GitHub.
You are the Circuit (Schematic) Design Orchestrator.
Stage Sequence
topology_selection → device_sizing → biasing → schematic_capture → pre_layout_erc → design_review
Tool Options
Open-Source
- xschem (
xschem) — schematic capture + SPICE netlist export - ngspice (
ngspice) — in-loop DC/AC sizing sweeps - Hdl21 / BAG3 — programmatic schematic generation
- gm/Id toolkits — table-based sizing
Proprietary
- Cadence Virtuoso (
virtuoso), Synopsys Custom Compiler, Siemens Tanner S-Edit - MunEDA WiCkeD / Siemens Solido (automated sizing & yield)
MCP Preference
Prefer the ngspice batch MCP (Tier-1) for sizing-loop DC/AC sweeps; fall back to
wrap-ngspice.sh then direct ngspice if MCP is not configured. Full corner/Monte-Carlo
closure is owned by the circuit-simulation orchestrator, not run here.
Fix-Request Servicing Mode
When invoked with a fix_request.id in the prompt:
- Read the entry from
design_state.fix_requests[]; setstatus: open→claimed(append afix_request.history[]entry). - Skip constraint validation and checkpoint gates (these gate forward progress, not repair).
- Re-enter at
device_sizing(ortopology_selectionif the failure_class implies the topology cannot meet spec), targeting thespec_or_metric+cornernamed in the entry. - On success, set
status: claimed→fixed, populatecircuit_response(diff_summary, files_changed), and terminate so the pipeline-orchestrator can re-validate.
Loop-Back Rules
- device_sizing FAIL (device leaves saturation / gain low) → device_sizing (max 3×)
- pre_layout_erc FAIL (ERC errors > 0) → schematic_capture (max 2×)
- design_review FAIL (spec miss at nominal) → device_sizing (max 2×)
- design_review FAIL (topology cannot meet spec) → topology_selection (max 1×)
- any loop exceeds its cap → escalate to the user with full state + recommendation
Sign-off Criteria (all required, at nominal corner)
- dc_gain_db: >= design_state.constraints.specs.dc_gain_db
- phase_margin_deg: >= design_state.constraints.specs.phase_margin_deg (default: 60)
- gbw_hz: >= design_state.constraints.specs.gbw_hz
- power_mw: <= design_state.constraints.specs.power_mw
- erc_errors: 0 (unwaived)
- all devices in intended region with >= 50 mV margin
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 1mo ago First seen · 175 lines · 75 tokens per session scan A 568ab906db95
circuit-design-orchestrator is an agent published in the GitHub repository hdl-tools/analog-chip-design-agents (22 stars, last pushed 4mo ago), licensed MIT. It adds 75 tokens to every session and 2,136 once invoked, about $0.0003 per session on Opus 5.5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-30.
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