Command Claude Code
Verible lint check on filelist.f — fail on any error.
AI-native Chiplet design flow based on open-source EDA toolchain
This repository also configures its own agents. See what Babel tells them →
Command Claude Code
Verible lint check on filelist.f — fail on any error.
Command Claude Code
KLayout GDSII export / DRC / verify wrapper.
Command Claude Code
Magic layout tool wrapper — floorplan/place/drc/extract. Direct invocation of bb-invoke-magic.
Command Claude Code
Netgen LVS wrapper — compare synth netlist vs Magic-extracted SPICE.
Command Claude Code
OpenSTA static timing analysis wrapper — synth-stage or post-PD multi-corner signoff. Direct invocation of bb-invoke-opensta.
Command Claude Code
QRouter detail routing wrapper.
Command Claude Code
Verilator simulation wrapper — compile RTL + TB and run coverage-driven sim. Direct invocation of the bb-invoke-verilator skill for debugging.
Command Claude Code
Yosys synthesis wrapper — synthesize RTL to ASAP7 netlist + QoR. Direct invocation of the bb-invoke-yosys skill for debugging.
Command Claude Code
List Babel handoff issues by label. Direct invocation of bb-list-issues.
Command Claude Code
Run bba-architect on a design idea. Drives bb-prd → bb-arch → bb-mas → adapter → spec-review → ready-for-rtl handoff.
Command Claude Code
Run bba-guru-pd. floorplan → place → route → DRC → LVS → post-PD STA → GDSII export.
Command Claude Code
Run bba-guru-rtl on a ready-for-rtl handoff. MAS → SystemVerilog + filelist.f + rtlartifact.json.
Command Claude Code
Run bba-guru-synthesis. Drafts SDC, runs CDC+RDC, yosys synthesis + opensta to timing closure.
Command Claude Code
Run bba-guru-verification on a ready-for-verification handoff. RTL + verifplanseed → 100% functional + code coverage.
Command Claude Code
A command that extracts structured test points from MAS, verifplanseed, or verificationplan files into JSON and Markdown. The output describes checks that later tools can turn into hardware tests.
Command Claude Code
A command that creates a per-module SystemVerilog testbench harness from test points and RTL ports. The harness includes basic simulation structure, coverage setup, and lint support.
Command Claude Code
A command that turns test points into executable SystemVerilog test cases, a test registry, and a script for running them. SystemVerilog is a language commonly used to describe and test digital hardware.
At most 3 mods per repository are shown here, and a mod shipped inside a plugin is left to that plugin's page — the rest are on their repository pages: