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bjwanneng/veriflow-cc

VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilog/Yosys) using a stateful, zero-dependency LLM orchestration skill. Features sub-agent nesting for code gen and behavioral-driven verification.

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veriflow-cc CLAUDE.md

01

bjwanneng/veriflow-cc

Instructions file

Claude Code instructions for bjwanneng/veriflow-cc, covering claude.md, project: veriflow-cc, mandatory: plan before code, mandatory: tdd (test-driven development) and test location.

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