rtl-skills: Instructions file for Claude Code

RTL Design Project

Project Overview

This is an RTL design project for developing hardware modules in Verilog. The project includes RTL source code, reusable library modules, documentation generated during development, and project files for simulation and synthesis.

Project Structure

.
├── CLAUDE.md              // project instructions (this file)
├── flow_status.md         // live phase-completion snapshot (written by vflow)
├── ddoc/                  // per-module requirement files, inputs for vdesign
├── doc/                   // generated module and IP documentation
├── lib/                   // reusable RTL library modules
│   ├── module_1.v         // single-file library module
│   ├── module_1.md        // documentation for module_1
│   └── module_2/          // multi-file library module
│       ├── module_2.v     // top-level RTL
│       ├── any.v          // submodule used by module_2
│       └── module_2.md    // documentation for module_2
├── rtl/                   // RTL code developed for this project
│   ├── module_m.v
│   └── module_n.v
├── tb/                    // testbenches
│   ├── <module>/          // unit testbench generated by vfill
│   │   └── <module>_tb.sv //   (per-submodule lint/sim during implementation)
│   └── <ip>/              // IP-level bench project scaffolded by vtestgen
│       ├── Makefile       //   top dispatcher, auto-discovers tb_*.sv
│       ├── script/
│       │   ├── library.mk //   per-testcase xvlog/xelab/xsim recipe
│       │   └── rtl.f      //   generated RTL hierarchy filelist
│       ├── clock.vh       //   parameterized clock + sync-reset generators
│       ├── dut.vh         //   reg-map, DUT instance, CPU BFM tasks + sequences
│       ├── sti_<iface>.sv //   CPU-controllable stimulus driver per data iface
│       ├── sco_<iface>.sv //   CPU-controllable scoreboard per stream output (optional)
│       ├── tb_<name>.sv   //   self-checking testcases (CPU-bus only)
│       ├── tc_list.md     //   testcase index with status
│       └── sim/<tc>/      //   disposable build dirs (compile/elaborate/sim logs)
├── issue/                 // failure reports and debug reports
│   └── <ip_name>/
│       ├── issue_NNN_<tcname>.md   // failure context (vtestrun)
│       ├── debug_NNN_<tcname>.md   // root cause diagnosis (vdebug)
│       ├── run_summary.md          // overall pass/fail count
│       └── debug_summary.md        // root cause grouping across issues
├── synth/                 // synthesis outputs generated by vsynth
│   └── <module>/
│       ├── vsynth.tcl     // Vivado synthesis script
│       ├── utilization.rpt
│       ├── timing_summary.rpt
│       ├── power.rpt
│       └── synth_report.md
└── prj/                   // simulation and synthesis project files