phamcuong21478

phamcuong21478/rtl-skills

Instructions file

Instructions for phamcuong21478/rtl-skills, covering rtl design project, project overview, project structure, design workflow and available skills.

phamcuong21478/rtl-skills

Skill Claude CodeCodex

Decompose an IP requirement into submodules, define interfaces, and generate an architecture document plus per-module requirement files and a top-level skeleton.

phamcuong21478/rtl-skills

Skill Claude CodeCodex

Trace failing signals through the RTL hierarchy, classify root cause, and write a debug report per issue — no fix is proposed.

phamcuong21478/rtl-skills

Skill Claude CodeCodex

Generate a design proposal, documentation, and RTL backbone from a requirement file.

phamcuong21478/rtl-skills

Skill Claude CodeCodex

Aggregate all per-module documentation into a single comprehensive IP document.

phamcuong21478/rtl-skills

Skill Claude CodeCodex

Generate documentation for any RTL module from Verilog source files.

phamcuong21478/rtl-skills

Skill Claude CodeCodex

Implement Verilog code from an approved design proposal, then lint and simulate.

phamcuong21478/rtl-skills

Skill Claude CodeCodex

Scan project state to determine phase completion, write flowstatus.md, and orchestrate the full RTL design flow from architecture to documentation.

phamcuong21478/rtl-skills

Skill Claude CodeCodex

Synthesize a Verilog module or full IP with Vivado and report resource utilization, Fmax, and power.

phamcuong21478/rtl-skills

Skill Claude CodeCodex

Scaffold a Makefile-driven, CPU-bus-controlled testbench project for an IP and generate a comprehensive set of self-checking testcases, validate each with make, and write a testcase list.

phamcuong21478/rtl-skills

Skill Claude CodeCodex

Run all IP-level testcases from tclist.md through the bench Makefile, capture results, and write per-failure issue reports with no fix suggestions.