Getting it into your agent
It runs from inside its repository, so the clone comes first — what it calls does not travel with the file alone.
git clone --depth 1 https://github.com/phamcuong21478/rtl-skillsnpx agentmods add skills/phamcuong21478/rtl-skills/vsynthWrote this? Show the measurements
A badge with what this costs and how it scanned, read live from this page, so it follows the numbers instead of freezing them. Markdown for a README, HTML for a documentation site or a project page.
[](https://agentmods.dev/skills/phamcuong21478/rtl-skills/vsynth)<a href="https://agentmods.dev/skills/phamcuong21478/rtl-skills/vsynth"><img src="https://agentmods.dev/badge/skills/phamcuong21478/rtl-skills/vsynth/github.svg" alt="Measured on agentmods" height="20"></a>Or the 80×15 button, for a site that already has a row of RSS and ATOM ones. Only the verdict fits; the numbers stay here.
<a href="https://agentmods.dev/skills/phamcuong21478/rtl-skills/vsynth"><img src="https://agentmods.dev/badge/skills/phamcuong21478/rtl-skills/vsynth.svg" alt="Reviewed on agentmods" width="80" height="20"></a>What it costs to keep this loaded
Counted locally with the o200k_base tokenizer, which is exact for GPT models; Claude uses its own tokenizer and its counts differ. Treat this as one consistent yardstick across the catalogue rather than a bill. Prices are per million input tokens.
| Model | Per session | Once invoked |
|---|---|---|
| Fable 5.1 | $0.00025 | $0.02619 |
| Opus 5 | $0.00013 | $0.01309 |
| Sonnet 5 | $0.00005 | $0.00524 |
| Haiku 4.5 | $0.00003 | $0.00262 |
Grade A, and why
vsynth scanned grade A with 0 findings against 26 rules in 11 categories — prompt injection, anti-refusal, data exfiltration, privilege escalation, supply chain, agent snooping, system-prompt leakage, SSRF and excessive agency — measured 12d ago.
A static scan of the body, not an audit. Every finding is printed with the line that produced it so you can judge whether it matters here. A mod is markdown that instructs an agent; that is exactly why what it instructs is worth reading.
Nothing flagged
None of the 26 patterns this scan looks for appear in this file: no shell pipes, no recursive deletes, no credential paths, no hidden text, no instruction-override or anti-refusal phrasing, no agent-config snooping. That is not a guarantee, it is the absence of the things that are checkable.
How it starts
The opening of the file, as written. The whole thing — 287 lines — stays where its author put it; the contents beside it link to each section on GitHub.
Verilog Synthesizer
Overview
This guide defines the workflow for running Vivado out-of-context (OOC) synthesis on a single module or a full IP hierarchy and producing a structured synthesis report.
The input is a module or IP name. The outputs are:
- A Vivado TCL synthesis script in
synth/<module>/ - Raw Vivado report files (utilization, timing, power)
- A structured synthesis report
synth/<module>/synth_report.md
Prerequisites
| Tool | Purpose | Check |
|---|---|---|
| Vivado | Synthesis, optimization, and reporting | vivado -version |
Before running synthesis, verify Vivado is installed using the check command
above. If it is missing, stop and report that Vivado is unavailable — never
fabricate utilization, timing, power, or Fmax results. Steps 1–4 (scope,
filelist, script generation) can still be done without the tool, but Steps 5–7
must not be reported as completed unless synthesis actually ran. (When invoked
under vflow, this surfaces as ✗ BLOCKED (tool unavailable: vivado) for the
Synthesis phase.)
Arguments
The skill takes a module or IP name. Optional overrides may follow as
key=value pairs:
part=<vivado_part>— target device (defaultxczu7ev-ffvc1156-2-e)period=<ns>— clock constraint period in ns (default2.800)
Example: vsynth foo_top part=xc7a100t-csg324-1 period=5.0. When no overrides
are given, use the defaults in Step 4.
Before You Start — Re-run Safety
Check whether synth/<module>/synth_report.md already exists:
| State | Detect | Action |
|---|---|---|
| First run | no synth/<module>/synth_report.md |
Generate the script and run synthesis normally. |
| Already synthesized | report exists | Do not silently re-synthesize. Re-run only if the user explicitly asks, an argument override changed (part/period), or an RTL source in the hierarchy is newer than the report (find <sources> -newer synth/<module>/synth_report.md). Otherwise report the existing result and stop. When you do re-run, overwrite the prior outputs in place rather than accumulating stale files. |
What this file has done since we first saw it
Hashed on every crawl. A supply-chain change to an agent config is a question of when, not whether, so the history is kept rather than the latest state alone.
- 12d ago First seen · 287 lines · 25 tokens per session scan A 56724dfb6f60
vsynth is a skill published in the GitHub repository phamcuong21478/rtl-skills (13 stars, last pushed 3mo ago), licensed Apache-2.0. It adds 25 tokens to every session and 2,619 once invoked, about $0.0001 per session on Opus 5. A static security scan graded it A with 0 findings. No closer match exists in the catalogue, so it is treated as the original; first seen 2026-08-31.
Other skills, from other repositories
simulation
Use when materializing and running a module's UVM TB from an approved verification plan (regression, coverage); not for plan authoring or RTL changes.
simulation-plan
Use when generating or evolving the verification plan, scaffold specification, testpoints, and power scenarios for a module; not for materializing UVM TB or running EDA tools.
synthesis
Use when running Design Compiler synthesis, analyzing timing/area/power reports, supplementing SDC exceptions, or re-synthesizing after RTL changes; not for power analysis or static timing.
design-flow
Use when progressing IC design through stages, checking module status, or routing rework decisions; not for single-stage execution or artifact authoring.
lint-cdc
Use when running SpyGlass lint or CDC checks, analyzing violations, adding waivers, supplementing SGDC annotations, or re-running after RTL changes; not for synthesis or simulation.
power-analysis
Use when running gate-level power simulation + PT-PX averaged power analysis (SAIF flow) for PPA gating; not for RTL functional simulation, static timing, or time-resolved waveforms.