24 tagged chip design, measured the same way as everything else here.
Browse within: rtl-design 22systemverilog 22rtl 10verilog 10
Skill Claude CodeCodex
Use this skill to start or resume the VeriFlow RTL hardware design pipeline (architect to synth). Trigger this when the user asks to "run the RTL flow", "design hardware", or "start the pipeline". Pass the project directory path as the argument. Optional: append --benchmark to auto-generate a benchmark report after…
The-OpenROAD-Project/OpenROAD-MCP
Skill Claude CodeCodex
Prepare a new version release for the openroad-mcp project. Automates version bumping, changelog generation, lockfile updates, and release commit creation. Use this skill whenever the user asks to: Prepare a release, cut a release, or do a release Bump the version or update the version Create a release commit Ship a…
Skill Claude CodeCodex
Decompose an IP requirement into submodules, define interfaces, and generate an architecture document plus per-module requirement files and a top-level skeleton.
Skill Claude CodeCodex
Generate a design proposal, documentation, and RTL backbone from a requirement file.
Skill Claude CodeCodex
Implement Verilog code from an approved design proposal, then lint and simulate.
Skill Claude CodeCodex
Use when a simulation run fails and root-cause analysis is needed before a rework decision; not for fixing code, modifying state, or running regression.
Skill Claude CodeCodex
Use when materializing and running a module's UVM TB from an approved verification plan (regression, coverage); not for plan authoring or RTL changes.
Skill Claude CodeCodex
Use when running Design Compiler synthesis, analyzing timing/area/power reports, supplementing SDC exceptions, or re-synthesizing after RTL changes; not for power analysis or static timing.